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Hwang-Cherng Chow: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng
    A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:736-739 [Conf]
  2. Hwang-Cherng Chow, I-Chyn Wey
    A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:121-124 [Conf]
  3. Hwang-Cherng Chow
    Bidirectional buffer for mixed voltage applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:270-273 [Conf]
  4. Hwang-Cherng Chow, Shu-Hsien Chang
    High performance sense amplifier circuit for low power SRAM applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:741-744 [Conf]
  5. Hwang-Cherng Chow, I-Chyn Wey
    A 3.3 V 1 GHz high speed pipelined Booth multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:457-460 [Conf]
  6. Hwang-Cherng Chow, Yung-Kuo Ho
    New pixel-shared design and split-path readout of CMOS image sensor circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:49-52 [Conf]

  7. A Low Voltage Rail-to-Rail OPAMP Design for Biomedical Signal Filtering Applications. [Citation Graph (, )][DBLP]


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