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Publications of Author

1. Omar M. Al-Jarrah, Ali Shatnawi, Alaa Halawani
   Recognition of gestures in arabic sign language using neural networks. [Citation Graph (0, 0)][DBLP]
   Artificial Intelligence and Soft Computing, 2006, pp:132-137 [Conf]
   
2. Ali Shatnawi
   A Flow-Based Algorithm for Computing the Iteration Bound in Recursive Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
   International Conference on Computational Intelligence, 2004, pp:345-348 [Conf]
   
3. Ali Shatnawi, M. Omair Ahmad, M. N. S. Swamy
   Rate-Optimal Static Scheduling of DSP Data Flow Graphs onto Multiprocessors using Circuit Contraction. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1995, pp:1360-1363 [Conf]
   
4. Ali Shatnawi, M. Omair Ahmad, M. N. S. Swamy
   Scheduling of DSP data flow graphs onto multiprocessors for maximum throughput. [Citation Graph (0, 0)][DBLP]
   ISCAS (6), 1999, pp:386-389 [Conf]
   
5. C. Duanmu, M. Omair Ahmad, M. N. S. Swamy, Ali Shatnawi
   A vector based fast block motion estimation algorithm for implementation on SIMD architectures. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2002, pp:337-340 [Conf]
   
6. Awni Itradat, M. Omair Ahmad, Ali Shatnawi
   A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
   PARELEC, 2006, pp:386-391 [Conf]
   
7. Ali Shatnawi, M. Omair Ahmad, M. N. S. Swamy
   Optimal Scheduling of Digital Signal Processing Data-flow Graphs using Shortest-path Algorithms. [Citation Graph (0, 0)][DBLP]
   Comput. J., 2002, v:45, n:1, pp:88-100 [Journal]
   
8. Awni Itradat, M. Omair Ahmad, Ali Shatnawi
   Architectural Synthesis of DSP Applications with Dynamically Reconfigurable Functional Units. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:1037-1040 [Conf]
   
9. Ali Shatnawi, Jehad Ghanim, M. Omair Ahmad
   High level synthesis of integrated heterogeneous pipelined processing elements for DSP applications. [Citation Graph (0, 0)][DBLP]
   Computers & Electrical Engineering, 2004, v:30, n:8, pp:543-562 [Journal]
   
10. 
    Minimization of I/O Delay in the architectural synthesis of DSP data flow graphs. [Citation Graph (, )][DBLP]