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Julio Sahuquillo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González, José Duato
    Efficient Interconnects for Clustered Microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:291-0 [Conf]
  2. L. G. Cárdenas, José A. Gil, Josep Domènech, Julio Sahuquillo, Ana Pont
    Performance Comparison of a Web Cache Simulation Framework. [Citation Graph (0, 0)][DBLP]
    AINA, 2005, pp:281-284 [Conf]
  3. B. de la Ossa, José A. Gil, Julio Sahuquillo, Ana Pont
    Delfos: the Oracle to Predict NextWeb User's Accesses. [Citation Graph (0, 0)][DBLP]
    AINA, 2007, pp:679-686 [Conf]
  4. Salvador Petit, Julio Sahuquillo, Jose M. Such, David R. Kaeli
    Exploiting temporal locality in drowsy cache policies. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:371-377 [Conf]
  5. Josep Domènech, Julio Sahuquillo, Ana Pont, José A. Gil
    Design keys to adapt web prefetching algorithms to environment conditions. [Citation Graph (0, 0)][DBLP]
    COMSWARE, 2006, pp:- [Conf]
  6. Félix Buendía, Julio Sahuquillo, J. V. Benlloch, José A. Gil, M. Agustí, Paloma Díaz
    XEDU, A Framework for Developing XML-Based Didactic Resources. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2001, pp:427-434 [Conf]
  7. Josep Domènech, Ana Pont, Julio Sahuquillo, José A. Gil
    An Experimental Framework for Testing Web Prefetching Techniques. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2004, pp:214-221 [Conf]
  8. Julio Sahuquillo, Ana Pont
    Designing Competitive Coherence Protocols Taking Advantage of Reuse Information. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1378-1385 [Conf]
  9. Julio Sahuquillo, Ana Pont
    Impact of Reducing Miss Write Latencies in Multiprocessors with Two Level Cache. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10333-10336 [Conf]
  10. Julio Sahuquillo, Ana Pont
    The Filter Cache: A Run-Time Cache Management Approach1. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1424-1431 [Conf]
  11. J. C. Cano, Teresa Nachiondo Frinós, Julio Sahuquillo, Ana Pont, José A. Gil
    WWW Client/Server Traffic Characterization: A Proxy Server Point of View. [Citation Graph (0, 0)][DBLP]
    HICSS, 2000, pp:- [Conf]
  12. Josep Domènech, Julio Sahuquillo, José A. Gil, Ana Pont
    About the Heterogeneity of Web Prefetching Performance Key Metrics. [Citation Graph (0, 0)][DBLP]
    INTELLCOMM, 2004, pp:220-235 [Conf]
  13. L. G. Cárdenas, José A. Gil, Julio Sahuquillo, Ana Pont
    Emulating Web Cache Replacement Algorithms versus a Real System. [Citation Graph (0, 0)][DBLP]
    ISCC, 2005, pp:891-897 [Conf]
  14. Julio Sahuquillo, Ana Pont, Veljko M. Milutinovic
    The Filter Data Cache: A Tour Management Comparison with Related Split Data Cache Schemes Sensitive to Data Localities. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2000, pp:319-327 [Conf]
  15. Josep Domènech, Ana Pont, Julio Sahuquillo, José A. Gil
    Cost-Benefit Analysis of Web Prefetching Algorithms from the User's Point of View. [Citation Graph (0, 0)][DBLP]
    Networking, 2006, pp:1113-1118 [Conf]
  16. L. G. Cárdenas, Julio Sahuquillo, Ana Pont, José A. Gil
    The Multikey Web Cache Simulator: A Platform for Designing Proxy Cache Management Techniques. [Citation Graph (0, 0)][DBLP]
    PDP, 2004, pp:390-397 [Conf]
  17. Salvador Petit, Julio Sahuquillo, Ana Pont
    Characterizing Parallel Workloads to Reduce Multiple Writer Overhead in Shared Virtual Memory Systems. [Citation Graph (0, 0)][DBLP]
    PDP, 2002, pp:261-268 [Conf]
  18. Salvador Petit, Julio Sahuquillo, Ana Pont
    A Comparison Study of the HLRC-DU Protocol versus a HLRC Hardware Assisted Protocol. [Citation Graph (0, 0)][DBLP]
    PDP, 2005, pp:197-204 [Conf]
  19. Salvador Petit, Julio Sahuquillo, Ana Pont, David R. Kaeli
    Characterizing the Dynamic Behavior of Workload Execution in SVM systems. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2004, pp:230-237 [Conf]
  20. Josep Domènech, Julio Sahuquillo, José A. Gil, Ana Pont
    The Impact of the Web Prefetching Architecture on the Limits of Reducing User's Perceived Latency. [Citation Graph (0, 0)][DBLP]
    Web Intelligence, 2006, pp:740-744 [Conf]
  21. Raúl Peña-Ortiz, Julio Sahuquillo, Ana Pont, José A. Gil
    Modeling continuous changes of the user's dynamic behavior in the WWW. [Citation Graph (0, 0)][DBLP]
    WOSP, 2005, pp:175-180 [Conf]
  22. Julio Sahuquillo, Salvador Petit, Ana Pont, Veljko M. Milutinovic
    Exploring the performance of split data cache schemes on superscalar processors and symmetric multiprocessors. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2005, v:51, n:8, pp:451-469 [Journal]
  23. Josep Domènech, José A. Gil, Julio Sahuquillo, Ana Pont
    Web prefetching performance metrics: A survey. [Citation Graph (0, 0)][DBLP]
    Perform. Eval., 2006, v:63, n:9-10, pp:988-1004 [Journal]
  24. Salvador Petit, Julio Sahuquillo, Ana Pont, David R. Kaeli
    Addressing a workload characterization study to the design of consistency protocols. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2006, v:38, n:1, pp:49-72 [Journal]
  25. Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González
    On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:2, pp:130-144 [Journal]
  26. Josep Domènech, Ana Pont, Julio Sahuquillo, José A. Gil
    A user-focused evaluation of web prefetching algorithms. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 2007, v:30, n:10, pp:2213-2224 [Journal]

  27. VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors. [Citation Graph (, )][DBLP]


  28. An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions. [Citation Graph (, )][DBLP]


  29. Reducing the Number of Bits in the BTB to Attack the Branch Predictor Hot-Spot. [Citation Graph (, )][DBLP]


  30. Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors. [Citation Graph (, )][DBLP]


  31. A Scheduling Heuristic to Handle Local and Remote Memory in Cluster Computers. [Citation Graph (, )][DBLP]


  32. Extending a Multicore Multithread Simulator to Model Power-Aware Hard Real-Time Systems. [Citation Graph (, )][DBLP]


  33. Dynamic task set partitioning based on balancing memory requirements to reduce power consumption. [Citation Graph (, )][DBLP]


  34. The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures. [Citation Graph (, )][DBLP]


  35. A simple power-aware scheduling for multicore systems when running real-time applications. [Citation Graph (, )][DBLP]


  36. An hybrid eDRAM/SRAM macrocell to implement first-level data caches. [Citation Graph (, )][DBLP]


  37. Speculative Validation of Web Objects for Further Reducing the User-Perceived Latency. [Citation Graph (, )][DBLP]


  38. Referrer graph: a low-cost web prediction algorithm. [Citation Graph (, )][DBLP]


  39. Dynamic task set partitioning based on balancing resource requirements and utilization to reduce power consumption. [Citation Graph (, )][DBLP]


  40. Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. [Citation Graph (, )][DBLP]


  41. Applying the zeros switch-off technique to reduce static energy in data caches. [Citation Graph (, )][DBLP]


  42. An Empirical Study on Maximum Latency Saving in Web Prefetching. [Citation Graph (, )][DBLP]


  43. An execution-driven simulation tool for teaching cache memories in introductory computer organization courses. [Citation Graph (, )][DBLP]


  44. Understanding cache hierarchy interactions with a program-driven simulator. [Citation Graph (, )][DBLP]


  45. Web prefetch performance evaluation in a real environment. [Citation Graph (, )][DBLP]


  46. Leakage Current Reduction in Data Caches on Embedded Systems. [Citation Graph (, )][DBLP]


  47. Using current web page structure to improve prefetching performance. [Citation Graph (, )][DBLP]


  48. Dweb model: Representing Web 2.0 dynamism. [Citation Graph (, )][DBLP]


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