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Publications of Author

1. Ramon Canal, Joan-Manuel Parcerisa, Antonio González
   A Cost-Effective Clustered Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 1999, pp:160-168 [Conf]
   
2. Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González, José Duato
   Efficient Interconnects for Clustered Microarchitectures. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2002, pp:291-0 [Conf]
   
3. Joan-Manuel Parcerisa, Antonio González
   The Latency Hiding Effectiveness of Decoupled Access/Execute Processors. [Citation Graph (0, 0)][DBLP]
   EUROMICRO, 1998, pp:10293-10300 [Conf]
   
4. Ramon Canal, Joan-Manuel Parcerisa, Antonio González
   Dynamic Cluster Assignment Mechanisms. [Citation Graph (0, 0)][DBLP]
   HPCA, 2000, pp:133-0 [Conf]
   
5. Joan-Manuel Parcerisa, Antonio González
   The Synergy of Multithreading and Access/Execute Decoupling. [Citation Graph (0, 0)][DBLP]
   HPCA, 1999, pp:59-63 [Conf]
   
6. Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio González
   Memory Bank Predictors. [Citation Graph (0, 0)][DBLP]
   ICCD, 2005, pp:666-670 [Conf]
   
7. Antonio González, Mateo Valero, Nigel P. Topham, Joan-Manuel Parcerisa
   Eliminating Cache Conflict Misses through XOR-Based Placement Functions. [Citation Graph (0, 0)][DBLP]
   International Conference on Supercomputing, 1997, pp:76-83 [Conf]
   
8. Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González
   Selective predicate prediction for out-of-order processors. [Citation Graph (0, 0)][DBLP]
   ICS, 2006, pp:46-54 [Conf]
   
9. Joan-Manuel Parcerisa, Antonio González
   Reducing wire delay penalty through value prediction. [Citation Graph (0, 0)][DBLP]
   MICRO, 2000, pp:317-326 [Conf]
   
10. Ramon Canal, Joan-Manuel Parcerisa, Antonio González
    Dynamic Code Partitioning for Clustered Architectures. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2001, v:29, n:1, pp:59-79 [Journal]
    
11. Joan-Manuel Parcerisa, Antonio González
    Improving Latency Tolerance of Multithreading through Decoupling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:10, pp:1084-1094 [Journal]
    
12. Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González
    On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:2, pp:130-144 [Journal]
    
13. 
    Early Register Release for Out-of-Order Processors with RegisterWindows. [Citation Graph (, )][DBLP]
    
    
14. 
    Improving Branch Prediction and Predicated Execution in Out-of-Order Processors. [Citation Graph (, )][DBLP]