Conferences in DBLP
Edward P. Farrell , Noordin Ghani , Philip C. Treieaven A Concurrent Computer Architecture and a Ring Based Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Michael Owens , Mary Jane Irwin On-Line Algorithms for the Design of Pipeline Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Virgil D. Gligor Architectural Implementations of Abstract Data Type Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Ken Sakamura , Kiochi Nakano , Yoshio Kato , Hideo Aiso A New Approach to an Adaptive Computer - An Automatic Recovery Mechanism to Prevent the Occurance of Subtract Errors. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre Brandwajn , Jean-Alain Hernandez , René Joly , Philippe Kruchten Overview of the ARCADE System. [Citation Graph (0, 0)][DBLP ] Conf ] Roger B. Danneberg An Architecture with Many Operand Registers to Efficiently Execute Block-Structured Languages. [Citation Graph (0, 0)][DBLP ] Conf ] Henry Fuchs , Brian W. Johnson An Expanded Multiprocessor Architecture for Video Graphics. [Citation Graph (0, 0)][DBLP ] Conf ] C. V. W. Armstrong , N. A. Brans , H. M. Ahmed An Adaptive Multimicroprocessor Array Computing Structure for Radar Signal Processing Applications. [Citation Graph (1, 0)][DBLP ] Conf ] Bryan D. Ackland A Bit-Slice Cache Controller. [Citation Graph (0, 0)][DBLP ] Conf ] J. Archer Harris , David R. Smith Simulation Experiments on a Tree Organized Minicomputer. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Patterson , E. Scott Fehr , Carlo H. Séquin Design Considerations for the VLSI Processor of X-tree. [Citation Graph (0, 0)][DBLP ] Conf ] Eiichi Goto , Tetsuo Ida , Kei Hiraki FLATS, a Machine for Numerical, Symbolic and Associative Computing. [Citation Graph (0, 0)][DBLP ] Conf ] John D. Spragins , T. G. Lewis , Hossein Jafari Some Simplified Performance Modeling Techniques with Applications to a New Ring-Structured Microcomputer Network. [Citation Graph (0, 0)][DBLP ] Conf ] Kishor S. Trivedi , Timothy M. Sigmon A Performance Comparison of Optimally Designed Computer Systems with and without Virtual Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Tilak Agerwala , K. Mani Chandy , D. E. Lang A Modeling Approach and Design Tool for Pipelined Central Processors. [Citation Graph (0, 0)][DBLP ] Conf ] M. Sato , S. Nichikawa , K. Murakami , S. Takahira Dynamic Function Exchanging Mechanism in Poly-Processor System. [Citation Graph (0, 0)][DBLP ] Conf ] B. R. Borgerson , M. D. Godfrey , P. E. Hagerty , T. R. Rykken The Architecture of Sperry Univac 1100 Series Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hassan K. Reghbati An Efficient Time-Shared Link Processor for Supporting Communication in Parallel Systems with Dynamic Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Anand R. Tripathi , G. Jack Lipovski Packet Switching in Banyan Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Janak H. Patel Processor-Memory Interconnections for Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] B. I. Strom Proof of the Equivalent Realizability of a Time-Bound Arbiter and a Runt-Free Inertail Delay. [Citation Graph (0, 0)][DBLP ] Conf ] Mark A. Franklin , S. A. Kahn , M. J. Stucki Design Issues in the Development of a Modular Mutliprocessor Communications Network. [Citation Graph (0, 0)][DBLP ] Conf ] Mamoru Maekawa Experimental Polyprocessor System (EPOS) - Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Mamoru Maekawa Experimental Polyprocessor System (EPOS) - Operating System. [Citation Graph (0, 0)][DBLP ] Conf ] Tse-Yun Feng , Chuan-lin Wu , Dharma P. Agrawal A Microprocessor-Controlled Asynchronous Circuit Switching Network. [Citation Graph (0, 0)][DBLP ] Conf ] W. G. Rosocha , E. S. Lee Performance Enhancement of SISD Processors. [Citation Graph (0, 0)][DBLP ] Conf ] S. Diane Smith , Howard Jay Siegel An Emulator Network for SIMD Machine Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] 