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Chuan-lin Wu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chuan-lin Wu, Tse-Yun Feng
    The Universality of the Shuffle-Exchange Network. [Citation Graph (1, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:5, pp:324-332 [Journal]
  2. Nader Bagherzadeh, Seng-lai Heng, Chuan-lin Wu
    A Parallel Asynchronous Garbage Collection Algorithm for Distributed Systems. [Citation Graph (1, 12)][DBLP]
    IEEE Trans. Knowl. Data Eng., 1991, v:3, n:1, pp:100-107 [Journal]
  3. Dz-Ching Ju, Wai-Mee Ching, Chuan-lin Wu
    On Performance and Space Usage Improvements for Parallelized Compiled APL Code. [Citation Graph (0, 0)][DBLP]
    APL, 1991, pp:234-243 [Conf]
  4. Chuan-lin Wu
    DDBC - A Distributed Database Computer for Very Large Data Base Management. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1982, pp:24-27 [Conf]
  5. Yi-Hsiu Wei, Chuan-lin Wu
    Integrating RPC and Message Passing for Distributed Programming. [Citation Graph (0, 0)][DBLP]
    DCE Workshop, 1993, pp:192-206 [Conf]
  6. Jin Li, Chuan-lin Wu
    A modular growth architecture for an ATM switch. [Citation Graph (0, 0)][DBLP]
    ICCCN, 1995, pp:420- [Conf]
  7. Jin Li, Chuan-lin Wu
    A novel architecture for an ATM switch. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:340-345 [Conf]
  8. Manjai Lee, Eric Fiene, Chuan-lin Wu, Geoffrey Brown, Nader Bagherzadeh
    Network Facility for a Reconfigurable Computer Architecture. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1985, pp:264-271 [Conf]
  9. Jin Li, Chuan-lin Wu
    Design and implementation of a multicast-buffer ATM switch. [Citation Graph (0, 0)][DBLP]
    ICNP, 1995, pp:84-91 [Conf]
  10. W. Lynn Gallagher, Chuan-lin Wu
    Evaluation of a memory hierarchy for the MTS multithreaded processor. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1997, pp:346-351 [Conf]
  11. Geoffrey M. Brown, Chuan-lin Wu
    Operating System Kernel for a Reconfigurable Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:234-241 [Conf]
  12. Chung-Yang Chiang, Chuan-lin Wu
    Fail Safe Distributed Fault Diagnosis of Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:358-365 [Conf]
  13. Chung-Yang Chiang, Chuan-lin Wu
    Adaptive Checkpointing and Rollback in Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:400-403 [Conf]
  14. Hsiao-chen Chung, Chuan-lin Wu, James Rakes, Peter J. Zievers, Yin-Kuan Lin
    Design and Evaluation of a Multiprocessor Architecture with Decentralized Control. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:97-100 [Conf]
  15. Dz-Ching Ju, Chuan-lin Wu, Paul R. Carini
    The Synthesis of Array Functions and Its Use in Parallel Computation. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1992, pp:293-296 [Conf]
  16. Dz-Ching Ju, Chuan-lin Wu, Paul R. Carini
    Statement Merge: an Inter-Statement Optimization of Array Language Programs. [Citation Graph (0, 0)][DBLP]
    ICPP, 1994, pp:126-129 [Conf]
  17. Woei Lin, Chuan-lin Wu
    Configuring Computation Tree Topologies on a Distributed Computing System. [Citation Graph (0, 0)][DBLP]
    ICPP, 1983, pp:114-116 [Conf]
  18. Woei Lin, Chuan-lin Wu
    Design of Configuration Algorithms of Commonly-Used Topologies for a Multiprocessor : STAR. [Citation Graph (0, 0)][DBLP]
    ICPP, 1985, pp:734-741 [Conf]
  19. Karam Mossaad, Chuan-lin Wu
    Efficient Execution of Programs with Pipeline Configuration of Reconfigurable Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:552-554 [Conf]
  20. Terence M. Potter, Hsiao-chen Chung, Chuan-lin Wu
    Reconfigurable Branch Processing Strategy in Super-Scalar Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:47-50 [Conf]
  21. R. Guru Prasadh, Chuan-lin Wu
    A Benchmark Evaluation of a Multi-threaded RISC Processor Architecture. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:84-91 [Conf]
  22. Thang Tran, Chuan-lin Wu
    Microprocessor Architecture with Multi-Bit Scoreboard Concurrency Control. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:128-135 [Conf]
  23. Lingtao Wang, Chuan-lin Wu
    Distributed Instruction Set Computer. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:426-429 [Conf]
  24. Tse-Yun Feng, Chuan-lin Wu, Dharma P. Agrawal
    A Microprocessor-Controlled Asynchronous Circuit Switching Network. [Citation Graph (0, 0)][DBLP]
    ISCA, 1979, pp:202-215 [Conf]
  25. Woei Lin, Chuan-lin Wu
    Design of a 2 × 2 fault-tolerant switching element. [Citation Graph (0, 0)][DBLP]
    ISCA, 1982, pp:181-189 [Conf]
  26. Manjai Lee, Chuan-lin Wu
    Performance Analysis of Circuit Switching Baseline Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1984, pp:82-90 [Conf]
  27. Thang Tran, Chuan-lin Wu
    Limitation of superscalar microprocessor performance. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:33-36 [Conf]
  28. Avijit Saha, Jim Christian, Dun-Sung Tang, Chuan-lin Wu
    Oriented Non-Radial Basis Functions for Image Coding and Analysis. [Citation Graph (0, 0)][DBLP]
    NIPS, 1990, pp:728-734 [Conf]
  29. Lingtao Wang, Chuan-lin Wu
    I-NET mechanism for issuing multiple instructions. [Citation Graph (0, 0)][DBLP]
    SC, 1988, pp:88-95 [Conf]
  30. Chuan-lin Wu
    Interconnection Networks - Guest Editor's Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1981, v:14, n:12, pp:8-9 [Journal]
  31. Chuan-lin Wu
    Multiprocessing Technology - Guest Editor's Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1985, v:18, n:6, pp:6-7 [Journal]
  32. Geoffrey M. Brown, Mohamed G. Gouda, Chuan-lin Wu
    Token Systems that Self-Stabilize. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:6, pp:845-852 [Journal]
  33. Tse-Yun Feng, Chuan-lin Wu
    Fault-Diagnosis for a Class of Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:10, pp:743-758 [Journal]
  34. Woei Lin, Chuan-lin Wu
    Reconfiguration Procedures for a Polymorphic and Partitionable Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:10, pp:910-916 [Journal]
  35. Woei Lin, Chuan-lin Wu
    A Distributed Resource Management Mechanism for a Partitionable Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:2, pp:201-210 [Journal]
  36. Woei Lin, Chuan-lin Wu
    A Fault-Tolerant Mapping Scheme for a Configurable Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:2, pp:227-237 [Journal]
  37. Woei Lin, Tsang-Ling Sheu, Chita R. Das, Tse-Yun Feng, Chuan-lin Wu
    A Conflict-Free Routing Scheme on Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:8, pp:1086-1097 [Journal]
  38. Avijit Saha, Chuan-lin Wu, Dun-Sung Tang
    Approximation, Dimension Reduction, and Nonconvex Optimization Using Linear Superpositions of Gaussians. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:10, pp:1222-1233 [Journal]
  39. Chao Chi Tong, Chuan-lin Wu
    Routing in a Three-Dimensional Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:1, pp:106-117 [Journal]
  40. Lingtao Wang, Chuan-lin Wu
    Distributed Instruction Set Computer Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:8, pp:915-934 [Journal]
  41. Chuan-lin Wu, Tse-Yun Feng
    On a Class of Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:8, pp:694-702 [Journal]
  42. Chuan-lin Wu, Tse-Yun Feng
    The Reverse-Exchange Interconnection Network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:9, pp:801-811 [Journal]
  43. Chuan-lin Wu, Tse-Yun Feng, Min-Chang Lin
    Star: A Local Network System for Real-Time Management of Imagery Data. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:10, pp:923-933 [Journal]
  44. Chuan-lin Wu, Manjai Lee
    Performance Analysis of Multistage Interconnection Network Configurations and Operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:1, pp:18-27 [Journal]
  45. Albert C. Chen, Chuan-lin Wu
    A Parallel Execution Model of Logic Programs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1991, v:2, n:1, pp:79-92 [Journal]
  46. Dz-Ching Ju, Chuan-lin Wu, Paul R. Carini
    The Classification, Fusion, and Parallelization of Array Language Primitives. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:10, pp:1113-1120 [Journal]

  47. A versatile VLSI fast Fourier transform processor. [Citation Graph (, )][DBLP]


  48. Distributed circuit switching starnet. [Citation Graph (, )][DBLP]


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