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José L. Núñez-Yáñez: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger Goodall, Tanya Vladimirova
    A Novel Processor Architecture for Real-Time Control. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:270-280 [Conf]
  2. Tom R. Jacobs, José L. Núñez-Yáñez
    A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:405-410 [Conf]
  3. José L. Núñez-Yáñez, Vassilios A. Chouliaras
    Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:411-416 [Conf]
  4. Vassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. Kumaraswamy, José L. Núñez-Yáñez
    Configurable Multiprocessors for High-Performance MPEG-4 Video Coding. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:272-273 [Conf]
  5. K. Koutsomyti, S. R. Parr, Vassilios A. Chouliaras, J. Nuñez
    Applying data-parallel and scalar optimizations for the efficient implementation of the G.729A and G.723.1 speech coding standards. [Citation Graph (0, 0)][DBLP]
    SIP, 2005, pp:39-44 [Conf]
  6. José L. Núñez-Yáñez, Vassilios A. Chouliaras
    A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:11, pp:1345-1359 [Journal]
  7. R. Stapenhurst, K. Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan
    On the Hardware Reduction of z-Datapath of Vectoring CORDIC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3002-3005 [Conf]

  8. Fault-tolerant dynamically reconfigurable NoC-based SoC. [Citation Graph (, )][DBLP]


  9. Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration. [Citation Graph (, )][DBLP]


  10. Dynamic Voltage Scaling in a FPGA-based System-on-Chip. [Citation Graph (, )][DBLP]


  11. Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor. [Citation Graph (, )][DBLP]


  12. Run-time resource management in fault-tolerant network on reconfigurable chips. [Citation Graph (, )][DBLP]


  13. A biophysically accurate floating point somatic neuroprocessor. [Citation Graph (, )][DBLP]


  14. Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. [Citation Graph (, )][DBLP]


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