Conferences in DBLP
Title Page. [Citation Graph (0, 0)][DBLP ] Conf ] Program Committee. [Citation Graph (0, 0)][DBLP ] Conf ] External Referees. [Citation Graph (0, 0)][DBLP ] Conf ] Message from the Conference Chairs. [Citation Graph (0, 0)][DBLP ] Conf ] Conference Organizers. [Citation Graph (0, 0)][DBLP ] Conf ] Copyright Page. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Flynn Area - Time - Power and Design effort: the basic tradeoffs in Application Specific Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Schlichter , Christian Haubelt , Frank Hannig , Jürgen Teich Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Claudiu Zissulescu , Bart Kienhuis , Ed F. Deprettere Expression Synthesis in Process Networks generated by LAURA. [Citation Graph (0, 0)][DBLP ] Conf ] Bharath N , Nagaraju Bussa Artificial Deadlock Detection in Process Networks for ECLIPSE. [Citation Graph (0, 0)][DBLP ] Conf ] Alain Darte , Steven Derrien , Tanguy Risset Hardware/Software Interface for Multi-Dimensional Processor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Kiyofumi Tanaka Casablanca II: Implementation of a Real-Time RISC. [Citation Graph (0, 0)][DBLP ] Conf ] Jérôme Lemaitre , Sylvain Alliot , Ed F. Deprettere Behavioral specification of control interface for signal processing applications. [Citation Graph (0, 0)][DBLP ] Conf ] Michalis D. Galanis , Grigoris Dimitroulakos , Costas E. Goutis Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Karim Ben Chehida , Michel Auguin A SW/Configware Codesign Methodology for Control Dominated Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Samarjit Chakraborty Towards a Framework for System-Level Design of Multiprocessor SoC Platforms for Media Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Ümit Y. Ogras , Jingcao Hu , Radu Marculescu Communication-Centric SoC Design for Nanoscale Domain. [Citation Graph (0, 0)][DBLP ] Conf ] Sudeep Pasricha , Mohamed Ben-Romdhane Using TLM for Exploring Bus-based SoC Communication Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe Ascia , Vincenzo Catania , Maurizio Palesi , Davide Patti Exploring Design Space of VLIW Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Stamatis Vassiliadis , Leonel Sousa , Georgi Gaydadjiev The Midlifekicker Microarchitecture Evaluation Metric. [Citation Graph (0, 0)][DBLP ] Conf ] Jayaprakash Pisharath , Alok N. Choudhary Design of a Hardware Accelerator for Density Based Clustering Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Adrian Burian , Perttu Salmela , Jarmo Takala Complex Fixed-Point Matrix Inversion Using Transport Triggered Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Kuo-Kun Tseng , Ying-Dar Lin , Tsern-Huei Lee , Yuan-Cheng Lai A Parallel Automaton String Matching with Pre-Hashing and Root-Indexing Techniques for Content Filtering Coprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Enrico Ng , Gyungho Lee Eliminating Sorting in IP Lookup Devices using Partitioned Table. [Citation Graph (0, 0)][DBLP ] Conf ] Ludovic L'Hours Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Moboluwaji O. Sanu , Earl E. Swartzlander Jr. Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos Kavvadias , Spiridon Nikolaidis Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding. [Citation Graph (0, 0)][DBLP ] Conf ] Jan-Willem van de Waerdt , Stamatis Vassiliadis Instruction Set Architecture Enhancements for Video Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Md. Mostafizur Rahman Mozumdar , Kingshuk Karuri , Anupam Chattopadhyay , Stefan Kraemer , Hanno Scharwächter , Heinrich Meyr , Gerd Ascheid , Rainer Leupers Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Grigoris Dimitroulakos , Michalis D. Galanis , Costas E. Goutis Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Byeong Kil Lee , Lizy Kurian John , Eugene John Architectural Support for Accelerating Congestion Control Applications in Network Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Andy Lambrechts , Praveen Raghavan , Anthony Leroy , Guillermo Talavera , Tom Vander Aa , Murali Jayapala , Francky Catthoor , Diederik Verkest , Geert Deconinck , Henk Corporaal , Frédéric Robert , Jordi Carrabina Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application. [Citation Graph (0, 0)][DBLP ] Conf ] Aristides Efthymiou , Jim D. Garside , Ioannis Papaefstathiou A Low-Power Processor Architecture Optimized forWireless Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Vida Kianzad , Shuvra S. Bhattacharyya , Gang Qu CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yang Yang , Tong Jing , Xianlong Hong , Yu Hu , Qi Zhu , Xiaodong Hu , Guiying Yan Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. [Citation Graph (0, 0)][DBLP ] Conf ] Thi Nguyen , Kaijian Shi Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Plessl , Marco Platzner Zippy - A coarse-grained reconfigurable array with support for hardware virtualization. [Citation Graph (0, 0)][DBLP ] Conf ] Amilcar do Carmo Lucas , Rolf Ernst An Image Processor for Digital Film. [Citation Graph (0, 0)][DBLP ] Conf ] João M. P. Cardoso On Estimations for Compiling Software to FPGA-based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Hosein Kamalizad , Nozar Tabrizi , Nader Bagherzadeh , Akira Hatanaka A Programmable DSP Architecture for Wireless Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Fidjeland , Wayne Luk Customising Application-Speci.c Multiprocessor Systems: a Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Han , Erin Taylor , Jianbo Gao , José A. B. Fortes Faults, Error Bounds and Reliability of Nanoelectronic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Maria J. Avedillo , José M. Quintana , Héctor Pettenghi Logic Models Supporting the Design of MOBILE-based RTD Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sorin Cotofana , Alexandre Schmid , Yusuf Leblebici , A. Ionescu , Oliver Soffke , Peter Zipf , Manfred Glesner , A. Rubio CONAN - A Design Exploration Framework for Reliable Nano-Electronics. [Citation Graph (0, 0)][DBLP ] Conf ] Bjørn Jager , Jörg-Christian Niemann , Ulrich Rückert Analytical approach to massively parallel architectures for nanotechnologies. [Citation Graph (0, 0)][DBLP ] Conf ] Valeriu Beiu , Snorre Aunet , Jabulani Nyathi , Ray Robert Rydberg III , Asbjørn Djupdal On the Advantages of Serial Architectures for Low-Power Reliable Computations. [Citation Graph (0, 0)][DBLP ] Conf ] P. M. Kelly , T. Martin McGinnity , Liam P. Maguire Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Konrad Walus , Mike Mazur , Gabriel Schulhof , Graham A. Jullien Simple 4-Bit Processor Based On Quantum-Dot Cellular Automata (QCA). [Citation Graph (0, 0)][DBLP ] Conf ] Cor Meenderinck , Sorin Cotofana , Casper Lageweg High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Luc Beuchat , Jean-Michel Muller Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement. [Citation Graph (0, 0)][DBLP ] Conf ] Liang-Kai Wang , Michael J. Schulte Decimal Floating-Point Square Root Using Newton-Raphson Iteration. [Citation Graph (0, 0)][DBLP ] Conf ] Milos D. Ercegovac , Jean-Michel Muller Variable Radix Real and Complex Digit-Recurrence Division. [Citation Graph (0, 0)][DBLP ] Conf ] Julio Villalba , Javier Hormigo , Jose M. Prades , Emilio L. Zapata On-line Multioperand Addition Based on On-line Full Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Jérémie Detrey , Florent de Dinechin Table-based polynomials for fast hardware function evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Romain Michard , Arnaud Tisserand , Nicolas Veyrat-Charvillon Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Eberle , Arvinderpal Wander , Nils Gura , Sheueling Chang Shantz , Vipul Gupta Architectural Extensions for Elliptic Curve Cryptography over GF(2m ) on 8-bit Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Lejla Batina , Nele Mentens , Bart Preneel , Ingrid Verbauwhede Side-channel aware design: Algorithms and Architectures for Elliptic Curve Cryptography over GF(2n ). [Citation Graph (0, 0)][DBLP ] Conf ] A. Murat Fiskiran , Ruby B. Lee On-Chip Lookup Tables for Fast Symmetric-Key Encryption. [Citation Graph (0, 0)][DBLP ] Conf ] Suman Mamidi , Daniel Iancu , Andrei Iancu , Michael J. Schulte , John Glossner Instruction Set Extensions for Reed-Solomon Encoding and Decoding. [Citation Graph (0, 0)][DBLP ] Conf ] Perttu Salmela , Tuomas Järvinen , Teemu Sipilä , Jarmo Takala 256-State Rate 1/2 Viterbi Decoder on TTA Processor. [Citation Graph (0, 0)][DBLP ] Conf ] M. Van Der Horst , Kees van Berkel , Johan Lukkien , Rudolf H. Mak Recursive Filtering on a Vector DSP with Linear Speedup. [Citation Graph (0, 0)][DBLP ] Conf ] Ian Steiner , P. Chan , Laurent Imbert , Graham A. Jullien , Vassil S. Dimitrov , G. H. McGibney A Fault-Tolerant Modulus Replication Complex FIR Filter. [Citation Graph (0, 0)][DBLP ] Conf ] Asadollah Shahbahrami , Ben H. H. Juurlink , Stamatis Vassiliadis Performance Comparison of SIMD Implementations of the Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Michael T. Frederick , Nathan A. VanderHorn , Arun K. Somani Real-time H/W Implementation of the Approximate Discrete Radon Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Tom R. Jacobs , José L. Núñez-Yáñez A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] José L. Núñez-Yáñez , Vassilios A. Chouliaras Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec. [Citation Graph (0, 0)][DBLP ] Conf ] 