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Publications of Author

1. Christian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber
   FPGA Implementation of a Novel Architecture for PCR Related Measurements In DVB-T. [Citation Graph (0, 0)][DBLP]
   ESA/VLSI, 2004, pp:606-610 [Conf]
   
2. Michael Janiaut, Camel Tanougast, Hassan Rabah, Yves Berviller, Christian Mannino, Serge Weber
   Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:386-390 [Conf]
   
3. Christian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber
   FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:1027-1031 [Conf]
   
4. Sylvain Poussier, Hassan Rabah, Serge Weber
   SOPC-based Embedded Smart Strain Gage Sensor. [Citation Graph (0, 0)][DBLP]
   FPL, 2002, pp:1131-1134 [Conf]
   
5. Domingo Torres, Hervé Mathias, Hassan Rabah, Serge Weber
   SIMD/restricted MIMD parallel architecture for Image Processing Based on a New Design of a Multi-mode Access Memory. [Citation Graph (0, 0)][DBLP]
   PDPTA, 1999, pp:567-570 [Conf]
   
6. Camel Tanougast, Yves Berviller, Christian Mannino, Hassan Rabah, Michael Janiaut, Serge Weber
   SystemC Model of a MPEG-2 DVB-T Bit-Rate Measurement Architecture for FPGA Implementation. [Citation Graph (0, 0)][DBLP]
   IEEE International Workshop on Rapid System Prototyping, 2004, pp:157-163 [Conf]
   
7. Hassan Rabah, Hervé Mathias, Serge Weber, E. Mozef, Camel Tanougast
   Linear array processors with multiple access modes memory for real-time image processing. [Citation Graph (0, 0)][DBLP]
   Real-Time Imaging, 2003, v:9, n:3, pp:205-213 [Journal]
   
8. Camel Tanougast, Yves Berviller, Philippe Brunet, Serge Weber, Hassan Rabah
   Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2003, v:27, n:3, pp:115-130 [Journal]
   
9. 
   Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC. [Citation Graph (, )][DBLP]
   
   
10. 
    An Auto-adaptation Method for Dynamically Reconfigurable System-on-Chip. [Citation Graph (, )][DBLP]
    
    
11. 
    Auto-adaptive reconfigurable architecture for scalable multimedia applications. [Citation Graph (, )][DBLP]
    
    
12. 
    Linear array processors with multiple access modes memory for real-time image processing. [Citation Graph (, )][DBLP]