The SCEAS System
Navigation Menu

Conferences in DBLP

Field-Programmable Logic and Applications (FPL) (fpl)
2004 (conf/fpl/2004)

  1. Wim Roelandts
    FPGAs and the Era of Field Programmability. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1- [Conf]
  2. Nick Tredennick, Brion Shimamoto
    Reconfigurable Systems Emerge. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:2-11 [Conf]
  3. Mark Dickinson
    System-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE? [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:12- [Conf]
  4. Anish Alex, Jonathan Rose, Ruth Isserlin-Weinberger, Christopher W. V. Hogue
    Hardware Accelerated Novel Protein Identification. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:13-22 [Conf]
  5. Stefan Dydel, Piotr Bala
    Large Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:23-32 [Conf]
  6. Jonathan Graf, Peter M. Athanas
    A Key Management Architecture for Securing Off-Chip Data Transfers. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:33-42 [Conf]
  7. Celia López-Ongil, Raul Sánchez-Reillo, Judith Liu-Jimenez, Fernando Casado, Leslie Sánchez, Luis Entrena
    FPGA Implementation of Biometric Authentication System Based on Hand Geometry. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:43-53 [Conf]
  8. Tero Rissa, Peter Y. K. Cheung, Wayne Luk
    SoftSONIC: A Customisable Modular Platform for Video Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:54-63 [Conf]
  9. A. Bigot, F. Charpentier, Helena Krupnova, I. Sans
    Deploying Hardware Platforms for SoC Validation: An Industrial Case Study. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:64-73 [Conf]
  10. Tim Kerins, Emanuel M. Popovici, William P. Marnane
    Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:74-83 [Conf]
  11. François-Xavier Standaert, Siddika Berna Örs, Jean-Jacques Quisquater, Bart Preneel
    Power Analysis Attacks Against FPGA Implementations of the DES. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:84-94 [Conf]
  12. Maya Gokhale, Janette Frigo, Christine Ahrens, Justin L. Tripp, Ronald Minnich
    Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:95-104 [Conf]
  13. Masato Yoshimi, Yasunori Osana, Tomonori Fukushima, Hideharu Amano
    Stochastic Simulation for Biochemical Reactions on FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:105-114 [Conf]
  14. Alexander Thomas, Jürgen Becker
    Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:115-124 [Conf]
  15. Frederick C. Furtek, Eugene Hogenauer, James Scheuermann
    Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:125-134 [Conf]
  16. Michael Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini
    Improving FPGA Performance and Area Using an Adaptive Logic Module. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:135-144 [Conf]
  17. Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan
    A Dual-VDD Low Power FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:145-157 [Conf]
  18. Gang Chen, Jason Cong
    Simultaneous Timing Driven Clustering and Placement for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:158-167 [Conf]
  19. Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng
    Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:168-178 [Conf]
  20. Andrea Lodi, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Fabio Campi, Mario Toma
    Compact Buffered Routing Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:179-188 [Conf]
  21. Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung, Jiping Liu
    On Optimal Irregular Switch Box Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:189-199 [Conf]
  22. Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides
    Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:200-208 [Conf]
  23. Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps
    Comparative Study of SRT-Dividers in FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:209-220 [Conf]
  24. Jérémie Detrey, Florent de Dinechin
    Second Order Function Approximation Using a Single Multiplication on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:221-230 [Conf]
  25. Guerric Meurice de Dormale, Philippe Bulens, Jean-Jacques Quisquater
    Efficient Modular Division Implementation: ECC over GF(p) Affine Coordinates Application. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:231-240 [Conf]
  26. Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos
    A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:241-250 [Conf]
  27. Sebastian Lange, Martin Middendorf
    The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:251-260 [Conf]
  28. Minoru Watanabe, Fuminori Kobayashi
    A High-Density Optically Reconfigurable Gate Array Using Dynamic Method. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:261-269 [Conf]
  29. Didier Keymeulen, Ricardo Salem Zebulum, Adrian Stoica, Vu Duong, Michael I. Ferguson
    Evolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable Device. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:270-278 [Conf]
  30. Eduardo Picatoste-Olloqui, Francisco Cardells-Tormo, Jordi Sempere-Agulló, Atilà Herms-Berenguer
    Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:279-288 [Conf]
  31. Fatih Kocan, Jason Meyer
    Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:289-300 [Conf]
  32. David V. Schuehler, John W. Lockwood
    A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:301-310 [Conf]
  33. Zachary K. Baker, Viktor K. Prasanna
    Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:311-321 [Conf]
  34. Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko
    BIST Based Interconnect Fault Location for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:322-332 [Conf]
  35. A. Parreira, João Paulo Teixeira, Marcelino B. Santos
    FPGAs BIST Evaluation. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:333-343 [Conf]
  36. C. J. Tavares, C. Bungardean, G. M. Matos, José T. de Sousa
    Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:344-353 [Conf]
  37. Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe
    Evaluating Fault Emulation on FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:354-363 [Conf]
  38. Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne Luk
    Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:364-373 [Conf]
  39. Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
    Multiple Restricted Multiplication. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:374-383 [Conf]
  40. Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez, Antonio García
    Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:384-393 [Conf]
  41. Christos-Savvas Bouganis, Peter Y. K. Cheung, Jeffrey Ng, Anil A. Bharath
    A Steerable Complex Wavelet Construction and Its Implementation on FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:394-403 [Conf]
  42. Gordon J. Brebner
    Programmable Logic Has More Computational Power than Fixed Logic. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:404-413 [Conf]
  43. Alexandra Poetter, Jesse Hunter, Cameron Patterson, Peter M. Athanas, Brent E. Nelson, Neil Steiner
    JHDLBits: The Merging of Two Worlds. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:414-423 [Conf]
  44. Changchun Shi, James Hwang, Scott McMillan, Ann Root, Vinay Singh
    A System Level Resource Estimation Tool for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:424-433 [Conf]
  45. Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
    The PowerPC Backend Molen Compiler. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:434-443 [Conf]
  46. Manish Handa, Ranga Vemuri
    An Integrated Online Scheduling and Placement Methodology. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:444-453 [Conf]
  47. Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker
    On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:454-463 [Conf]
  48. Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu Suzuki
    Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:464-473 [Conf]
  49. Marcos R. Boschetti, Sergio Bampi, Ivan Saraiva Silva
    Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:474-483 [Conf]
  50. Yutaka Sugawara, Mary Inaba, Kei Hiraki
    Over 10Gbps String Matching Mechanism for Multi-stream Packet Scanning Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:484-493 [Conf]
  51. Ma José Canet, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat, Eduardo R. de Lima
    Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:494-504 [Conf]
  52. Yoshiki Yamaguchi, Tsutomu Maruyama, Akihiko Konagaya
    Three-Dimensional Dynamic Programming for Homology Search. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:505-515 [Conf]
  53. Shin'ichi Wakabayashi, Kenji Kikuchi
    An Instance-Specific Hardware Algorithm for Finding a Maximum Clique. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:516-525 [Conf]
  54. Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong
    IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:526-535 [Conf]
  55. Mark Holland, Scott Hauck
    Automatic Creation of Reconfigurable PALs/PLAs for SoC. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:536-545 [Conf]
  56. Daniel Denning, James Irvine, Malachy Devlin
    A Key Agile 17.4 Gbit/sec Camellia Implementation. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:546-554 [Conf]
  57. Viktor Fischer, Milos Drutarovský, Martin Simka, Nathalie Bochard
    High Performance True Random Number Generator in Altera Stratix FPLDs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:555-564 [Conf]
  58. Norbert Pramstaller, Johannes Wolkerstorfer
    A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:565-574 [Conf]
  59. Joseph Zambreno, David Nguyen, Alok N. Choudhary
    Exploring Area/Delay Tradeoffs in an AES FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:575-585 [Conf]
  60. Sandeep S. Kumar, Christof Paar
    Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:586-595 [Conf]
  61. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:596-605 [Conf]
  62. Dalia Dagher, Iyad Ouaiss
    Storage Allocation for Diverse FPGA Memory Specifications. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:606-616 [Conf]
  63. Javier Díaz, Eduardo Ros, Sonia Mota, Richard R. Carrillo, Rodrigo Agís
    Real Time Optical Flow Processing System. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:617-626 [Conf]
  64. Tim Todman, Wayne Luk
    Methods and Tools for High-Resolution Imaging. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:627-636 [Conf]
  65. Andrei Bartic, Dirk Desmet, Jean-Yves Mignolet, Théodore Marescaux, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, J. Miller, Frédéric Robert
    Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:637-647 [Conf]
  66. Christophe Layer, Hans-Jörg Pfleiderer
    A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:648-657 [Conf]
  67. Sumit Mohanty, Viktor K. Prasanna
    A Framework for Energy Efficient Design of Multi-rate Applications Using Hybrid Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:658-668 [Conf]
  68. Jawad Khan, Ranga Vemuri
    An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:669-678 [Conf]
  69. Holger Lange, Andreas Koch
    HW/SW Co-design by Automatic Embedding of Complex IP Cores. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:679-689 [Conf]
  70. Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
    Increasing Pipelined IP Core Utilization in Process Networks Using Exploration. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:690-699 [Conf]
  71. Rawat Siripokarpirom
    Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:700-709 [Conf]
  72. Arthur Segard, François Verdier
    SOC and RTOS: Managing IPs and Tasks Communications. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:710-718 [Conf]
  73. Steven J. E. Wilton, Su-Shin Ang, Wayne Luk
    The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:719-728 [Conf]
  74. Jingzhao Ou, Viktor K. Prasanna
    A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:729-739 [Conf]
  75. Rajarshi Mukherjee, Seda Ogrenci Memik
    Power-Driven Design Partitioning. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:740-750 [Conf]
  76. Michael G. Lorenz, Luis Mengibar, Mario García-Valderas, Luis Entrena
    Power Consumption Reduction Through Dynamic Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:751-760 [Conf]
  77. Mihail Petrov, Tudor Murgan, F. May, Martin Vorbach, Peter Zipf, Manfred Glesner
    The XPP Architecture and Its Co-simulation Within the Simulink Environment. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:761-770 [Conf]
  78. Muhammad Atif Tahir, Ahmed Bouridane, Fatih Kurugollu
    An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:771-780 [Conf]
  79. Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek
    Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:781-790 [Conf]
  80. Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller
    Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS - High Energy Physics Experiment. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:791-800 [Conf]
  81. Brandon Blodget, Christophe Bobda, Michael Hübner, Adronis Niyonkuru
    Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:801-810 [Conf]
  82. Adam Donlin, Axel Braun, Adam Rose
    SystemC for the Design and Modeling of Programmable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:811-820 [Conf]
  83. Jim Torresen
    An Evolvable Hardware Tutorial. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:821-830 [Conf]
  84. Herbert Walder, Marco Platzner
    A Runtime Environment for Reconfigurable Hardware Operating Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:831-835 [Conf]
  85. Xin Jia, Jayanthi Rajagopalan, Ranga Vemuri
    A Dynamically Reconfigurable Asynchronous FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:836-841 [Conf]
  86. Björn Griese, Erik Vonnahme, Mario Porrmann, Ulrich Rückert
    Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:842-846 [Conf]
  87. Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen
    Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:847-851 [Conf]
  88. Alexander Danilin, Sergei Sawitzki
    Optimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:852-856 [Conf]
  89. Shawn Phillips, Akshay Sharma, Scott Hauck
    Automating the Layout of Reconfigurable Subsystems via Template Reduction. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:857-861 [Conf]
  90. Tom Van Court, Yongfeng Gu, Martin C. Herbordt
    FPGA Acceleration of Rigid Molecule Interactions. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:862-867 [Conf]
  91. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:868-873 [Conf]
  92. Cristinel Ababei, Pongstorn Maidee, Kia Bazargan
    Exploring Potential Benefits of 3D FPGA Integration. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:874-880 [Conf]
  93. Yang Qu, Kari Tiensyrjä, Kostas Masselos
    System-Level Modeling of Dynamically Reconfigurable Co-processors. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:881-885 [Conf]
  94. João Canas Ferreira, José Silva Matos
    A Development Support System for Applications That Use Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:886-890 [Conf]
  95. Nikhil Bansal, Sumit Gupta, Nikil D. Dutt, Alexandru Nicolau, Rajesh K. Gupta
    Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:891-899 [Conf]
  96. Renqiu Huang, Manish Handa, Ranga Vemuri
    Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:900-905 [Conf]
  97. Hossam A. ElGindy, George Ferizis
    Mapping Basic Recursive Structures to Runtime Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:906-910 [Conf]
  98. Takehiro Ito, Yuichiro Shibata, Kiyoshi Oguri
    Implementation of the Extended Euclidean Algorithm for the Tate Pairing on FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:911-916 [Conf]
  99. Martin Schoeberl
    Java Technology in an FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:917-921 [Conf]
  100. Valery Sklyarov, Iouliia Skliarova, Bruno S. Pimentel, Joel Arrais
    Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:922-926 [Conf]
  101. Chrilly Donninger, Ulf Lorenz
    The Chess Monster Hydra. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:927-932 [Conf]
  102. Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe
    FPGA-Efficient Hybrid LUT/CORDIC Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:933-937 [Conf]
  103. Oliver A. Pfänder, Roland Hacker, Hans-Jörg Pfleiderer
    A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:938-942 [Conf]
  104. Cesar Torres-Huitzil, René Cumplido-Parra, Santos López-Estrada
    Design and Implementation of a CFAR Processor for Target Detection. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:943-947 [Conf]
  105. Joseph Palmer, Brent E. Nelson
    A Parallel FFT Architecture for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:948-953 [Conf]
  106. Marcos Martínez Peiró, Francisco Ballester, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer
    FPGA Custom DSP for ECG Signal Analysis and Compression. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:954-958 [Conf]
  107. Quoc Thai Ho, Daniel Massicotte
    FPGA Implementation of Adaptive Multiuser Detector for DS-CDMA Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:959-964 [Conf]
  108. Unai Bidarte, Armando Astarloa, José Luis Martín, Jon Andreu
    Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:965-969 [Conf]
  109. Erik Schüler, Luigi Carro
    A Low Power FPAA for Wide Band Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:970-974 [Conf]
  110. Edson L. Horta, John W. Lockwood
    Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:975-979 [Conf]
  111. Tsutomu Maruyama
    Real-Time Computation of the Generalized Hough Transform. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:980-985 [Conf]
  112. Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides
    Minimum Sum of Absolute Differences Implementation in a Single FPGA Device. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:986-990 [Conf]
  113. Faycal Bensaali, Abbes Amira
    Design and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed Arithmetic. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:991-995 [Conf]
  114. Jesús Lázaro, Armando Astarloa, Jagoba Arias, Unai Bidarte, Carlos Cuadrado
    High Throughput Serpent Encryption Implementation. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:996-1000 [Conf]
  115. Sashisu Bajracharya, Chang Shu, Kris Gaj, Tarek A. El-Ghazawi
    Implementation of Elliptic Curve Cryptosystems over GF(2n) in Optimal Normal Basis on a Reconfigurable Computer. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1001-1005 [Conf]
  116. Hagen Gädke, Andreas Koch
    Wavelet-Based Image Compression on the Reconfigurable Computer ACE-V. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1006-1010 [Conf]
  117. María Dolores Valdés, Miguel A. Domínguez, María José Moure, Camilo Quintáns
    A Reconfigurable Communication Processor Compatible with Different Industrial Fieldbuses. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1011-1016 [Conf]
  118. Philip James-Roxby, Gordon J. Brebner
    Multithreading in a Hyper-programmable Platform for Networked Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1017-1021 [Conf]
  119. Ricardo Ferreira, João M. P. Cardoso, Horácio C. Neto
    An Environment for Exploring Data-Driven Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1022-1026 [Conf]
  120. Christian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber
    FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1027-1031 [Conf]
  121. Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich
    A Dynamic NoC Approach for Communication in Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1032-1036 [Conf]
  122. Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker
    Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1037-1041 [Conf]
  123. Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato
    FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1042-1046 [Conf]
  124. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    A Structured Methodology for System-on-an-FPGA Design. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1047-1051 [Conf]
  125. Kris Tiri, Ingrid Verbauwhede
    Secure Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1052-1056 [Conf]
  126. M. G. Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo
    Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1057-1061 [Conf]
  127. Jonathan Noel Tombs, Miguel Angel Aguirre Echánove, Fernando Muñoz Chavero, Vicente Baena Lecuyer, Antonio Jesús Torralba Silgado, A. Fernandez-León, Francisco Tortosa
    The Implementation of a FPGA Hardware Debugger System with Minimal System Overhead. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1062-1066 [Conf]
  128. Andrzej Krasniewski
    Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1067-1072 [Conf]
  129. Chris Clarke, Lin Qiang, Herbert Peremans, Álvaro Hernández
    FPGA Implementation of a Neuromimetic Cochlea for a Bionic Bat Head. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1073-1075 [Conf]
  130. Terrence S. T. Mak, K. P. Lam
    FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1076-1079 [Conf]
  131. Albert A. Conti, Tom Van Court, Martin C. Herbordt
    Processing Repetitive Sequence Structures with Mismatches at Streaming Rate. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1080-1083 [Conf]
  132. Pedro Ferreira, Pedro Ribeiro, Ana Antunes, Fernando Morgado Dias
    Artificial Neural Networks Processor - A Hardware Implementation Using a FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1084-1086 [Conf]
  133. Enrique Cantó, Nicolau Canyellas, Mariano Fons, Francisco Fons, Mariano López
    FPGA Implementation of the Ridge Line Following Fingerprint Algorithm. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1087-1089 [Conf]
  134. Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner
    A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1090-1092 [Conf]
  135. David Nguyen, Joseph Zambreno, Gokhan Memik
    Flow Monitoring in High-Speed Networks with 2D Hash Tables. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1093-1097 [Conf]
  136. Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä
    A VHDL Generator for Elliptic Curve Cryptography. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1098-1100 [Conf]
  137. Alessandro Bogliolo, Valerio Freschi, Filippo Miglioli, Matteo Canella
    FPGA-Based Parallel Comparison of Run-Length-Encoded Strings. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1101-1103 [Conf]
  138. Juan Manuel García Chamizo, Andrés Fuster Guilló, Jorge Azorín López
    Real Environments Image Labelling Based on Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1104-1106 [Conf]
  139. Jan Borgosz
    Object Oriented Programming Paradigms for the VHDL. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1107-1109 [Conf]
  140. Ivan Gonzalez, Javier Sanchez-Pastor, Jorge L. Hernandez-Ardieta, Francisco J. Gomez-Arribas, Javier Martínez
    Using Reconfigurable Hardware Through Web Services in Distributed Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1110-1112 [Conf]
  141. Nastaran Baradaran, Joonseok Park, Pedro C. Diniz
    Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1113-1115 [Conf]
  142. K. Siozios, G. Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis
    A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1116-1118 [Conf]
  143. Pierre Niang, Thierry Grandpierre, Mohamed Akil, Yves Sorel
    AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1119-1123 [Conf]
  144. Armando Astarloa, Jesús Lázaro, Unai Bidarte, José Luis Martín, Aitzol Zuloaga
    A Self-Reconfiguration Framework for Multiprocessor CSoPCs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1124-1126 [Conf]
  145. Adam Donlin, Patrick Lysaght, Brandon Blodget, Gerd Troeger
    A Virtual File System for Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1127-1129 [Conf]
  146. Tapio Ristimäki, Jari Nurmi
    Virtualizing the Dimensions of a Coarse-Grained Reconfigurable Array. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1130-1132 [Conf]
  147. Tomás Marek, Martin Novotný, Ludek Crha
    Design and Implementation of the Memory Scheduler for the PC-Based Router. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1133-1135 [Conf]
  148. Eric E. Fabris, Luigi Carro, Sergio Bampi
    Analog Signal Processing Reconfiguration for Systems-on-Chip Using a Fixed Analog Cell Approach. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1136-1138 [Conf]
  149. Luis Parrilla, Encarnación Castillo, Antonio García, Antonio Lloris-Ruíz
    Intellectual Property Protection for RNS Circuits on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1139-1141 [Conf]
  150. René de Jesús Romero-Troncoso, Gilberto Herrera Ruiz
    FPGA Implementation of a Tool Breakage Detection Algorithm in CNC Milling Machines. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1142-1145 [Conf]
  151. Milos Drutarovský, Viktor Fischer
    Implementation of a 3-D Switching Median Filtering Scheme with an Adaptive LUM-Based Noise Detector. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1146-1148 [Conf]
  152. Jan Schier, Antonin Hermanek
    Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1149-1151 [Conf]
  153. Viorela Ila, Rafael García, François Charot, Joan Batlle
    FPGA Implementation of a Vision-Based Motion Estimation Algorithm for an Underwater Robot. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1152-1154 [Conf]
  154. Hiroaki Niitsuma, Tsutomu Maruyama
    Real-Time Detection of Moving Objects. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1155-1157 [Conf]
  155. Sonia Mota, Eduardo Ros, Javier Díaz, Eva M. Ortigosa, Rodrigo Agís, Richard R. Carrillo
    Real-Time Visual Motion Detection of Overtaking Cars for Driving Assistance Using FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1158-1161 [Conf]
  156. Pierre Chalimbaud, François Berry
    Versatile Imaging Architecture Based on a System on Chip. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1162-1164 [Conf]
  157. Constantinos Skarpathiotis, Keith R. Dimond
    A Hardware Implementation of a Content Based Image Retrieval Algorithm. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1165-1167 [Conf]
  158. Ali Ahmadinia
    Optimization Algorithms for Dynamic Reconfigurable Embedded Systems p. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1168- [Conf]
  159. Aman Gayasen
    Low Power Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1169- [Conf]
  160. Brian F. Veale, John K. Antonio, Monte P. Tull
    Code Re-ordering for a Class of Reconfigurable Microprocessors. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1170- [Conf]
  161. Christian Haubelt
    Design Space Exploration for Distributed Hardware Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1171- [Conf]
  162. Cristinel Ababei
    TPR: Three-D Place and Route for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1172- [Conf]
  163. David B. Thomas, Wayne Luk
    Implementing Graphics Shaders Using FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1173- [Conf]
  164. Dirk Koch
    Preemptive Hardware Task Management. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1174- [Conf]
  165. Graham Schelle, Dirk Grunwald
    Automated Speculation and Parallelism in High Performance Network Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1175- [Conf]
  166. Heidi E. Ziegler
    Automated Mapping of Coarse-Grain Pipelined Applications to FPGA Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1176-1177 [Conf]
  167. Javier Resano
    A Specific Scheduling Flow for Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1178-1179 [Conf]
  168. Joseph Zambreno
    Design and Evaluation of an FPGA Architecture for Software Protection. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1180- [Conf]
  169. Mahim Mishra
    Scalable Defect Tolerance Beyond the SIA Roadmap. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1181-1182 [Conf]
  170. Mohamed Taher, Tarek A. El-Ghazawi
    Run-Time Reconfiguration Management for Adaptive High-Performance Computing Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1183- [Conf]
  171. Nalin Sidahao
    Optimized Field Programmable Gate Array Based Function Evaluation. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1184- [Conf]
  172. R. Manimegalai, A. Manoj Kumar, B. Jayaram, V. Kamakoti
    MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1185- [Conf]
  173. Ray C. C. Cheung
    A System on Chip Design Framework for Prime Number Validation Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1186-1187 [Conf]
  174. Terrence S. T. Mak, K. P. Lam
    On Computing Maximum Likelihood Phylogeny Using FPGA p. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1188- [Conf]
  175. Usama Malik
    Minimising Reconfiguration Overheads in Embedded Applications (Abstract). [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1189- [Conf]
  176. Vinu Vijay Kumar
    Application Specific Small-Scale Reconfigurability. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1190- [Conf]
  177. Zachary K. Baker
    Efficient FPGA-Based Security Kernels. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1191- [Conf]
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002