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Publications of Author

1. Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi
   A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. [Citation Graph (0, 0)][DBLP]
   DDECS, 2007, pp:247-250 [Conf]
   
2. Hassan Ghasemzadeh, Sepideh Sepideh Mazrouee, Mohammad Reza Kakoee
   Modified Pseudo LRU Replacement Algorithm. [Citation Graph (0, 0)][DBLP]
   ECBS, 2006, pp:368-376 [Conf]
   
3. Bijan Alizadeh, Mohammad Reza Kakoee
   Using Integer Equations for High Level Formal Verification Property Checking. [Citation Graph (0, 0)][DBLP]
   ISQED, 2003, pp:69-74 [Conf]
   
4. Mohammad Hossein Neishaburi, Masoud Daneshtalab, Mohammad Reza Kakoee, Saeed Safari
   Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors. [Citation Graph (0, 0)][DBLP]
   AICCSA, 2007, pp:528-534 [Conf]
   
5. Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi
   A New Approach for Design and Verification of Transaction Level Models. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:3760-3763 [Conf]
   
6. 
   De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. [Citation Graph (, )][DBLP]
   
   
7. 
   Functional Test-Case Generation by a Control Transaction Graph for TLM Verification. [Citation Graph (, )][DBLP]
   
   
8. 
   On-Chip Verification of NoCs Using Assertion Processors. [Citation Graph (, )][DBLP]
   
   
9. 
   Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification. [Citation Graph (, )][DBLP]
   
   
10. 
    A new physical routing approach for robust bundled signaling on NoC links. [Citation Graph (, )][DBLP]
    
    
11. 
    Automatic synthesis of near-threshold circuits with fine-grained performance tunability. [Citation Graph (, )][DBLP]
    
    
12. 
    Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions. [Citation Graph (, )][DBLP]