Conferences in DBLP
(ddecs) Daniel D. Gajski New Strategies for System-Level Design. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnendu Chakrabarty Design and Test of Microfluidic Biochips. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Rajski Logic Diagnosis and Yield Learning. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Bucci , Raimondo Luzzi A Testable Random Bit Generator Based on a High Resolution Phase Noise Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Jiri Jenícek , Ondrej Novák Test Pattern Compression Based on Pattern Overlapping. [Citation Graph (0, 0)][DBLP ] Conf ] Maksim Jenihhin , Jaan Raik , Raimund Ubar , Witold A. Pleskacz , Michal Rakowski Layout to Logic Defect Analysis for Hierarchical Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Bartosz Wojciechowski , Tomasz Kowalczyk , Wojciech Sakowski Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Radoslaw Czarnecki , Stanislaw Deniziak Resource Constrained Co-synthesis of Self-reconfigurable SOPCs. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Bernardi , Leticia Maria Veiras Bolzani , Matteo Sonza Reorda Extended Fault Detection Techniques for Systems-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Anders Larsson , Erik Larsson , Petru Eles , Zebo Peng A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing. [Citation Graph (0, 0)][DBLP ] Conf ] Saibal Mukhopadhyay , Qikai Chen , Kaushik Roy Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Benoît Godard , Jean Michel Daga , Lionel Torres , Gilles Sassatelli Architecture for Highly Reliable Embedded Flash Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Zhicheng Liang , Makoto Ikeda , Kunihiro Asada Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Maria Gkatziani , Rohit Kapur , Qing Su , Ben Mathew , Roberto Mattiuzzo , Laura Tarantini , Cy Hay , Salvatore Talluto , Thomas W. Williams Accurately Determining Bridging Defects from Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Ernest Jamro , Maciej Wielgosz , Kazimierz Wiatr FPGA Implementation of Strongly Parallel Histogram Equalization. [Citation Graph (0, 0)][DBLP ] Conf ] Grzegorz Borowik , Bogdan J. Falkowski , Tadeusz Luba Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Ari Kulmala , Erno Salminen , Timo D. Hämäläinen Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder. [Citation Graph (0, 0)][DBLP ] Conf ] Dongsoo Kim , Gunhee Han A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling. [Citation Graph (0, 0)][DBLP ] Conf ] Valeria Sipala , Domenico Lo Presti , Nunzio Randazzo , Luigi Caponetto A PMT Interface for the Optical Module Front-end of a Neutrino Underwater Telescope. [Citation Graph (0, 0)][DBLP ] Conf ] Santiago De Pablo , Santiago Cáceres , Jesús A. Cebrián , Manuel Berrocal A Proposal for ASM++ Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Piotr Buciak , Jakub Botwicz Lightweight Multi-threaded Network Processor Core in FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Torresen , Thor Arne Lovland Parts Obsolescence Challenges for the Electronics Industry. [Citation Graph (0, 0)][DBLP ] Conf ] Khalil Arshak , Francis Adepoju , Essa Jafer Simulation and Characterization of Wireless Data Acquisition RF Systems for Medical Diagnostic Application. [Citation Graph (0, 0)][DBLP ] Conf ] Ireneusz Brzozowski , Andrzej Kos Two-level Logic Synthesis for Low Power Based on New Model of Power Dissipation. [Citation Graph (0, 0)][DBLP ] Conf ] Gurgen Harutunyan , Valery A. Vardanian , Yervant Zorian A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Tomasz Garbolino , Krzysztof Gucwa , Michal Kopec , Andrzej Hlawiczka Avoiding Crosstalk Influence on Interconnect Delay Fault Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Tille , Görschwin Fey , Rolf Drechsler Instance Generation for SAT-based ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Khalil Arshak , Essa Jafer , Christian Ibala Power Testing of an FPGA-based System Using Modelsim Code Coverage Capability. [Citation Graph (0, 0)][DBLP ] Conf ] Ajoy Kumar Palit , Kishore K. Duganapalli , Walter Anheier XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Prashant Dubey , Akhil Garg , Sravan Kumar Bhaskarani Built in Defect Prognosis for Embedded Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Luigi Dilillo , Bashir M. Al-Hashimi March CRF: an Efficient Test for Complex Read Faults in SRAM Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Zaid Al-Ars , Said Hamdioui , Georgi Gaydadjiev Manifestation of Precharge Faults in High Speed DRAM Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Philipp Öhler , Sybille Hellebrand , Hans-Joachim Wunderlich Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Malík , Marcel Baláz , Tomás Pikula , Martin Simlastík An Improved MDCT IP Core Generator with Architectural Model Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Chiou-Kou Tung , Yu-Cherng Hung , Shao-Hui Shieh , Guo-Shing Huang A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System. [Citation Graph (0, 0)][DBLP ] Conf ] Tomás Martínek , Otto Fucík , Patrik Beck , Matej Lexa Automatic Generation of Circuits for Approximate String Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Costin Cepisca , Sorin Dan Grigorescu , Mircea Covrig , Horia Andrei About the Efficiency of Real Time Sequences FFT Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Simlastík , Viera Stopjaková , Libor Majer , Peter Malík Clockless Implementation of LEON2 for Low-Power Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Edward Hrynkiewicz , Stefan Kolodzinski Decomposition of Logic Functions in Reed-Muller Spectral Domain. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandru Amaricai , Mircea Vladutiu , Lucian Prodan , Mihai Udrescu , Oana Boncalo Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Torresen , Jorgen Norendal , Kyrre Glette Establishing a New Course in Reconfigurable Logic System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Artur L. Sobczyk , Arkadiusz W. Luczyk , Witold A. Pleskacz Power Dissipation in Basic Global Clock Distribution Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Roman Bazylevych , Ihor Podolskyy , Lubov Bazylevych Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre Rousset , Alberto Bosio , Patrick Girard , Christian Landrault , Serge Pravossoudovitch , Arnaud Virazel A Mixed Approach for Unified Logic Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Lukás Sekanina Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Hossein Neishaburi , Mohammad Reza Kakoee , Masoud Daneshtalab , Saeed Safari , Zainalabedin Navabi A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. [Citation Graph (0, 0)][DBLP ] Conf ] Sergei B. Musin , Alexander A. Ivaniuk , Vyacheslav N. Yarmolik Multiple Errors Detection Technique for RAM. [Citation Graph (0, 0)][DBLP ] Conf ] Tomasz Rudnicki , Andrzej Hlawiczka Test Pattern Generator for Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Oscar Ruano , Pilar Reyes , Juan A. Maestro , Luca Sterpone , Pedro Reviriego An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Giorgio Di Natale , Marie-Lise Flottes , Bruno Rouzeyre A Novel Parity Bit Scheme for SBox in AES Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Dariusz Koscielnik , Marek Miskowicz Designing Time-to-Digital Converter for Asynchronous ADCs. [Citation Graph (0, 0)][DBLP ] Conf ] Lukas Ruckay , Jirí Nedved Algorithm for DRM Signal Recognition in Time Domain and Hardware Realization. [Citation Graph (0, 0)][DBLP ] Conf ] Vytautas Dumbrava , Linas Svilainis RF Transformer Model Parameters Measurement. [Citation Graph (0, 0)][DBLP ] Conf ] Jorge Semião , J. Freijedo , Juan J. Rodríguez-Andina , Fabian Vargas , Marcelino B. Santos , Isabel C. Teixeira , João Paulo Teixeira Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel G. Gericota , Luís F. Lemos , Gustavo R. Alves , José M. Ferreira A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] René Kothe , Heinrich Theodor Vierhaus Flip-Flops and Scan-Path Elements for Nanoelectronics. [Citation Graph (0, 0)][DBLP ] Conf ] Pawel Pawlowski , Adam Dabrowski , Mario Schölzel Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair Facility via Variable Accuracy Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Pawel Russek , Kazimierz Wiatr Dedicated Architecture for Double Precision Matrix Multiplication in Supercomputing Environment. [Citation Graph (0, 0)][DBLP ] Conf ] András Timár , Márta Rencz Design Issues of a Low Frequency Low-Pass Filter for Medical Applications Using CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Havel , Karel Vlcek Feasibility of Image Compression in FPGA-based Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Antti Rasmus , Ari Kulmala , Erno Salminen , Timo D. Hämäläinen IP Integration Overhead Analysis in System-on-Chip Video Encoder. [Citation Graph (0, 0)][DBLP ] Conf ] Ábel Vámos Quadrature-Phase Topology of a High Frequency Ring Oscillator. [Citation Graph (0, 0)][DBLP ] Conf ] Rung-Bin Lin , Da-Wei Hsu , Ming-Hsine Kuo , Meng-Chiou Wu Reticle Exposure Plans for Multi-Project Wafers. [Citation Graph (0, 0)][DBLP ] Conf ] Gyula Bakonyi-Kiss , Zoltán Szucs Low Cost, Low Power, Intelligent Brake Temperature Sensor System for Automotive Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Bucher , Antonios Bazigos , Wladyslaw Grabinski Determining MOSFET Parameters in Moderate Inversion. [Citation Graph (0, 0)][DBLP ] Conf ] Tomasz Golonek , Damian Grzechca , Jerzy Rutkowski Evolutionary System for Analog Test Frequencies Selection with Fuzzy Initialization. [Citation Graph (0, 0)][DBLP ] Conf ] Pavel Kubalík , Jirí Kvasnicka , Hana Kubatova Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Korenek , Petr Kobierský Intrusion Detection System Intended for Multigigabit Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Wlodzimierz Jonca Open Defects Caused by Scratches and Yield Modelling in Deep Sub-micron Integrated Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardas Bareisa , Vacius Jusas , Kestutis Motiejunas , Rimantas Seinauskas Transition Faults Testing Based on Functional Delay Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Aristides Efthymiou Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yann Oddos , Katell Morin-Allory , Dominique Borrione Prototyping Generators for On-line Test Vector Generation Based on PSL Properties. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Herbstritt , Bernd Becker , Erika Ábrahám , Christian Herde On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Fabricio V. Andrade , Márcia C. M. Oliveira , Antônio Otávio Fernandes , Claudionor José Nunes Coelho Jr. SAT-Based Equivalence Checking Based on Circuit Partitioning and Special Approaches for Conflict Clause Reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Rogin , Erhard Fehlauer , Christian Haufe , Sebastian Ohnewald Debug Patterns for Efficient High-level SystemC Debugging. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas O. Shea , Ian Grout , Jeffrey Ryan Memory Based Analogue Signal Generation Implementation Issues for BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Petr Struhovský , Ondrej Subrt , Jirí Hospodka , Pravoslav Martínek Developing Virtual ADC Testing Environment in MAPLE. [Citation Graph (0, 0)][DBLP ] Conf ] Zbigniew Piatek , Jerzy F. Kolodziejski , Witold A. Pleskacz ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing. [Citation Graph (0, 0)][DBLP ] Conf ] Janos Mizsei , M. Reggente MEMS Testing by Vibrating Capacitor. [Citation Graph (0, 0)][DBLP ] Conf ] 