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Damian Dalton: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Damian Dalton, Vivian Bessler, Jeffrey Griffiths, Andrew McCarthy, Abhay Vadher, Rory O'Kane, Rob Quigley, Declan O'Connor
    APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1162-1165 [Conf]
  2. Damian Dalton
    Avoiding Conventional Overheads in Parallel Logic Simulation: A New Architecture. [Citation Graph (0, 0)][DBLP]
    HiPC, 1999, pp:364-370 [Conf]
  3. Damian Dalton
    Analysis of an Associative Array Parallel Logic Simulator. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 1999, pp:308-312 [Conf]
  4. Mario Polaschegg, Christian Steger, Damian Dalton, Abhay Vadher
    Parallel Simulation with a Generic Simulation Framework Featuring Loose Coupling. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2005, pp:251-257 [Conf]
  5. Alexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton
    Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:290-291 [Conf]
  6. Damian Dalton
    The Speedup Performance of an Associative Memory Based Logic Simulator. [Citation Graph (0, 0)][DBLP]
    PaCT, 1999, pp:207-216 [Conf]
  7. Alexander Maili, Damian Dalton, Christian Steger
    A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:799-808 [Conf]
  8. Damian Dalton
    A New Timing Mechanism Architecture for Discrete Logic Event Simulation. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:1236-1242 [Conf]

  9. A Generic Simulation Framework for Multiprocessor Architectures. [Citation Graph (, )][DBLP]

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