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Publications of Author

1. Gary William Grewal, Thomas Charles Wilson, C. Nell
   An Enhanced Genetic Algorithm Approach to the Channel Assignment Problem in Mobile Cellular Networks. [Citation Graph (0, 0)][DBLP]
   Canadian Conference on AI, 2002, pp:325-333 [Conf]
   
2. Peng Du, Gary William Grewal, Shawki Areibi, Dilip K. Banerji
   A Fast Hierarchical Approach to FPGA Placement. [Citation Graph (0, 0)][DBLP]
   ESA/VLSI, 2004, pp:497-503 [Conf]
   
3. Thomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji
   An ILP-based approach to code generation. [Citation Graph (0, 0)][DBLP]
   Code Generation for Embedded Processors, 1994, pp:103-118 [Conf]
   
4. Gary William Grewal
   A Global Mode Instruction Minimization Technique for Embedded DSPs. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1996, pp:18-0 [Conf]
   
5. Gary William Grewal, Mike O'Cleirigh, Charlie Obimbo
   Hierarchical Genetic Algorithms Applied to Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
   IC-AI, 2003, pp:994-1002 [Conf]
   
6. Gary William Grewal, Ming Xu, Charlie Obimbo
   An Approximate Solution for Steiner Trees in Multicast Routing. [Citation Graph (0, 0)][DBLP]
   IC-AI, 2004, pp:707-711 [Conf]
   
7. Thomas Charles Wilson, Gary William Grewal, Dilip K. Banerji
   An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis. [Citation Graph (0, 0)][DBLP]
   ICCD, 1994, pp:581-586 [Conf]
   
8. Gary William Grewal, Thomas Charles Wilson
   Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T). [Citation Graph (0, 0)][DBLP]
   MICRO, 2001, pp:192-202 [Conf]
   
9. Gary William Grewal, Thomas Charles Wilson
   An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1997, pp:51-56 [Conf]
   
10. Gary William Grewal, Thomas Charles Wilson, Ming Xu, Dilip K. Banerji
    Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:855-862 [Conf]
    
11. Thomas Charles Wilson, Gary William Grewal
    Shake And Bake: A Method of Mapping Code to Irregular DSPs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:506-508 [Conf]
    
12. Gary William Grewal, Thomas Charles Wilson
    An Enhanced Genetic Algorithm for Solving the High-Level Synthesis Problems of Scheduling, Allocation, and Binding. [Citation Graph (0, 0)][DBLP]
    International Journal of Computational Intelligence and Applications, 2001, v:1, n:1, pp:91-110 [Journal]
    
13. Gary William Grewal, Thomas Charles Wilson
    Mapping Reference Code to Irregular DSPS within the Retargetable, Optimizing Compiler Cogen(T). [Citation Graph (0, 0)][DBLP]
    International Journal of Computational Intelligence and Applications, 2003, v:3, n:1, pp:45-64 [Journal]
    
14. Shouvik Chowdhury, Gary William Grewal, Dilip K. Banerji
    Clustering Hanan Points to Reduce Vlsi Interconnect Routing Times. [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:1223-1227 [Conf]
    
15. 
    Hardware acceleration of Scatter Search. [Citation Graph (, )][DBLP]