The SCEAS System
Navigation Menu

Search the dblp DataBase


S. DasGupta: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. M. R. Brown, S. DasGupta
    Design of a general purpose meta-assembler for parallel processor environment in ISPS. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1989, pp:105-117 [Conf]
  2. S. DasGupta, H. Chang
    Simulation of a computer with variable hardware and variable instruction set. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1987, pp:1-12 [Conf]
  3. S. DasGupta, M. Hohenberger, Len Trejo, T. Kaylani
    Effect of data compression of ERP sign preprocessed by FWT algorithm upon a neural network classifier. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1990, pp:63-71 [Conf]
  4. F. Kampf, P. Koch, K. Roy, M. Sullivan, Z. Delalic, S. DasGupta
    Optimization of a digital neuron design. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1990, pp:73-80 [Conf]
  5. S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, D. Cottrell, D. Mallis, S. DasGupta, J. Morrell, J. Sayah, R. Gupta, P. T. Patel, P. Adams
    Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:257-260 [Conf]
  6. J. M. Hancock, S. DasGupta
    Tutorial on parallel processing for design automation applications (tutorial session). [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:69-77 [Conf]
  7. S. DasGupta, Kalapi Roy
    Description Language for a Neural Network Architecture. [Citation Graph (0, 0)][DBLP]
    IAS, 1989, pp:294-304 [Conf]
  8. R. Lopez-Valcarce, S. DasGupta
    Second order statistics based blind channel equalization with correlated sources. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:366-369 [Conf]
  9. R. Lopez-Valcarce, S. DasGupta
    Blind equalization of nonlinear digital satellite links with PSK modulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:409-412 [Conf]
  10. S. DasGupta
    Panel: Given that SEMATECH is levelling the semiconductor technology playing field, will corporate CAD (in particular, PD) tools continue to serve as enablers/differentiators of technology in the future? (panel). [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:86- [Conf]
  11. R. G. Bushroe, S. DasGupta, A. Dengi, P. Fisher, S. Grout, G. Ledenbach, N. S. Nagaraj, R. Steele
    Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:212-217 [Conf]
  12. S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, D. Cottrell, D. Mallis, S. DasGupta, J. Morrell, Amrich Chokhavtia
    CHDStd - application support for reusable hierarchical interconnect timing views. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:75-79 [Conf]
  13. Michael Collins, S. DasGupta, Robert E. Schapire
    A Generalization of Principal Components Analysis to the Exponential Family. [Citation Graph (0, 0)][DBLP]
    NIPS, 2001, pp:617-624 [Conf]

  14. Exact Fuzzy Modeling and Optimal control of a Launch Vehicle in the atmospheric phase. [Citation Graph (, )][DBLP]

Search in 0.002secs, Finished in 0.003secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002