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S. DasGupta :
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M. R. Brown , S. DasGupta Design of a general purpose meta-assembler for parallel processor environment in ISPS. [Citation Graph (0, 0)][DBLP ] Annual Simulation Symposium, 1989, pp:105-117 [Conf ] S. DasGupta , H. Chang Simulation of a computer with variable hardware and variable instruction set. [Citation Graph (0, 0)][DBLP ] Annual Simulation Symposium, 1987, pp:1-12 [Conf ] S. DasGupta , M. Hohenberger , Len Trejo , T. Kaylani Effect of data compression of ERP sign preprocessed by FWT algorithm upon a neural network classifier. [Citation Graph (0, 0)][DBLP ] Annual Simulation Symposium, 1990, pp:63-71 [Conf ] F. Kampf , P. Koch , K. Roy , M. Sullivan , Z. Delalic , S. DasGupta Optimization of a digital neuron design. [Citation Graph (0, 0)][DBLP ] Annual Simulation Symposium, 1990, pp:73-80 [Conf ] S. Grout , G. Ledenbach , R. G. Bushroe , P. Fisher , D. Cottrell , D. Mallis , S. DasGupta , J. Morrell , J. Sayah , R. Gupta , P. T. Patel , P. Adams Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 1998, pp:257-260 [Conf ] J. M. Hancock , S. DasGupta Tutorial on parallel processing for design automation applications (tutorial session). [Citation Graph (0, 0)][DBLP ] DAC, 1986, pp:69-77 [Conf ] S. DasGupta , Kalapi Roy Description Language for a Neural Network Architecture. [Citation Graph (0, 0)][DBLP ] IAS, 1989, pp:294-304 [Conf ] R. Lopez-Valcarce , S. DasGupta Second order statistics based blind channel equalization with correlated sources. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2001, pp:366-369 [Conf ] R. Lopez-Valcarce , S. DasGupta Blind equalization of nonlinear digital satellite links with PSK modulation. [Citation Graph (0, 0)][DBLP ] ISCAS (3), 2001, pp:409-412 [Conf ] S. DasGupta Panel: Given that SEMATECH is levelling the semiconductor technology playing field, will corporate CAD (in particular, PD) tools continue to serve as enablers/differentiators of technology in the future? (panel). [Citation Graph (0, 0)][DBLP ] ISPD, 1998, pp:86- [Conf ] R. G. Bushroe , S. DasGupta , A. Dengi , P. Fisher , S. Grout , G. Ledenbach , N. S. Nagaraj , R. Steele Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century. [Citation Graph (0, 0)][DBLP ] ISPD, 1997, pp:212-217 [Conf ] S. Grout , G. Ledenbach , R. G. Bushroe , P. Fisher , D. Cottrell , D. Mallis , S. DasGupta , J. Morrell , Amrich Chokhavtia CHDStd - application support for reusable hierarchical interconnect timing views. [Citation Graph (0, 0)][DBLP ] ISPD, 1998, pp:75-79 [Conf ] Michael Collins , S. DasGupta , Robert E. Schapire A Generalization of Principal Components Analysis to the Exponential Family. [Citation Graph (0, 0)][DBLP ] NIPS, 2001, pp:617-624 [Conf ] Exact Fuzzy Modeling and Optimal control of a Launch Vehicle in the atmospheric phase. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.002secs