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Conferences in DBLP

Automated Technology for Verification and Analysis (atva)
2007 (conf/atva/2007)

  1. Nathan Whitehead, Jordan Johnson, Martín Abadi
    Policies and Proofs for Code Auditing. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:1-14 [Conf]
  2. Atsushi Hasegawa
    Recent Trend in Industry and Expectation to DA Research. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:15-16 [Conf]
  3. Kenneth L. McMillan
    Toward Property-Driven Abstraction for Heap Manipulating Programs. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:17-18 [Conf]
  4. Sumit Nain, Moshe Y. Vardi
    Branching vs. Linear Time: Semantical Perspective. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:19-34 [Conf]
  5. Jörg Bauer, Tobe Toben, Bernd Westphal
    Mind the Shapes: Abstraction Refinement Via Topology Invariants. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:35-50 [Conf]
  6. Geng-Dian Huang, Bow-Yaw Wang
    Complete SAT-Based Model Checking for Context-Free Processes. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:51-65 [Conf]
  7. David Walter, Scott Little, Chris Myers
    Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:66-81 [Conf]
  8. Gordon J. Pace, Cristian Prisacariu, Gerardo Schneider
    Model Checking Contracts - A Case Study. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:82-97 [Conf]
  9. Gilles Geeraerts, Jean-François Raskin, Laurent Van Begin
    On the Efficient Computation of the Minimal Coverability Set for Petri Nets. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:98-113 [Conf]
  10. Scott Little, David Walter, Kevin Jones, Chris Myers
    Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:114-128 [Conf]
  11. Bijan Alizadeh, Masahiro Fujita
    Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:129-144 [Conf]
  12. Peter Habermehl, Radu Iosif, Adam Rogalewicz, Tomás Vojnar
    Proving Termination of Tree Manipulating Programs. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:145-161 [Conf]
  13. Marco Bozzano, Alessandro Cimatti, Francesco Tapparo
    Symbolic Fault Tree Analysis for Reactive Systems. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:162-176 [Conf]
  14. Thomas Gawlitza, Helmut Seidl
    Computing Game Values for Crash Games. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:177-191 [Conf]
  15. Franck Cassez, Alexandre David, Kim Guldstrand Larsen, Didier Lime, Jean-François Raskin
    Timed Control with Observation Based and Stuttering Invariant Strategies. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:192-206 [Conf]
  16. Lijun Zhang, Holger Hermanns
    Deciding Simulations on Probabilistic Automata. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:207-222 [Conf]
  17. Christian Dax, Jochen Eisinger, Felix Klaedtke
    Mechanizing the Powerset Construction for Restricted Classes of omega -Automata. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:223-236 [Conf]
  18. Zvonimir Rakamaric, Roberto Bruttomesso, Alan J. Hu, Alessandro Cimatti
    Verifying Heap-Manipulating Programs in an SMT Framework. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:237-252 [Conf]
  19. Sophie Pinchinat
    A Generic Constructive Solution for Concurrent Games with Expressive Constraints on Strategies. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:253-267 [Conf]
  20. Sven Schewe, Bernd Finkbeiner
    Distributed Synthesis for Alternating-Time Logics. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:268-283 [Conf]
  21. Indranil Saha, Janardan Misra, Suman Roy
    Timeout and Calendar Based Finite State Modeling and Verification of Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:284-299 [Conf]
  22. Dragan Bosnacki, Alastair F. Donaldson, Michael Leuschel, Thierry Massart
    Efficient Approximate Verification of Promela Models Via Symmetry Markers. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:300-315 [Conf]
  23. Orna Kupferman, Yoad Lustig
    Latticed Simulation Relations and Games. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:316-330 [Conf]
  24. Tingting Han, Joost-Pieter Katoen
    Providing Evidence of Likely Being on Time: Counterexample Generation for CTMC Model Checking. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:331-346 [Conf]
  25. Judi Romijn, Wieger Wesselink, Arjan J. Mooij
    Assertion-Based Proof Checking of Chang-Roberts Leader Election in PVS. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:347-361 [Conf]
  26. Laura Recalde, Serge Haddad, Manuel Silva
    Continuous Petri Nets: Expressive Power and Decidability Issues. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:362-377 [Conf]
  27. Edith Elkind, Blaise Genest, Doron Peled, Paola Spoletini
    Quantifying the Discord: Order Discrepancies in Message Sequence Charts. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:378-393 [Conf]
  28. Ismael Rodríguez, Manuel Núñez
    A Formal Methodology to Test Complex Heterogeneous Systems. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:394-409 [Conf]
  29. Rotem Oshman, Orna Grumberg
    A New Approach to Bounded Model Checking for Branching Time Logics. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:410-424 [Conf]
  30. Werner Damm, Stefan Disch, Hardi Hungar, Swen Jacobs, Jun Pang, Florian Pigorsch, Christoph Scholl, Uwe Waldmann, Boris Wirtz
    Exact State Set Representations in the Verification of Linear Hybrid Systems with Large Discrete State Space. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:425-440 [Conf]
  31. Hichem Boudali, Pepijn Crouzen, Mariëlle Stoelinga
    A Compositional Semantics for Dynamic Fault Trees in Terms of Interactive Markov Chains. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:441-456 [Conf]
  32. Orna Grumberg, Assaf Schuster, Avi Yadgar
    3-Valued Circuit SAT for STE with Automatic Refinement. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:457-473 [Conf]
  33. Sven Schewe, Bernd Finkbeiner
    Bounded Synthesis. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:474-488 [Conf]
  34. Moonzoo Kim
    Formal Modeling and Verification of High-Availability Protocol for Network Security Appliances. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:489-500 [Conf]
  35. Mercedes G. Merayo, Manuel Núñez, Ismael Rodríguez
    A Brief Introduction to THOTL. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:501-510 [Conf]
  36. Guoqiang Li, Mizuhito Ogawa
    On-the-Fly Model Checking of Fair Non-repudiation Protocols. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:511-522 [Conf]
  37. Bernard Berthomieu, Florent Peres, François Vernadat
    Model Checking Bounded Prioritized Time Petri Nets. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:523-532 [Conf]
  38. Salamah Salamah, Ann Q. Gates, Vladik Kreinovich, Steve Roach
    Using Patterns and Composite Propositions to Automate the Generation of LTL Specifications. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:533-542 [Conf]
  39. Muhammad Torabi Dashti, Anton Wijs
    Pruning State Spaces with Extended Beam Search. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:543-552 [Conf]
  40. Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
    Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:553-563 [Conf]
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