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Author:
Masahiro Fujita: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Masahiro Fujita, Takashi Kanai
    Precomputed Radiance Transfer with Spatially-Varying Lighting Effects. [Citation Graph (0, 0)][DBLP]
    CGIV, 2004, pp:101-108 [Conf]
  2. Masahiro Fujita, Gabriel Costa, Rika Hasegawa, Tsuyoshi Takagi, Jun Yokono, Hideki Shimomura
    Architecture and preliminary experimental results for emotionally grounded symbol acquisition. [Citation Graph (0, 0)][DBLP]
    Agents, 2001, pp:35-36 [Conf]
  3. Masahiro Fujita, Koji Kageyama
    An Open Architecture for Robot Entertainment. [Citation Graph (0, 0)][DBLP]
    Agents, 1997, pp:435-442 [Conf]
  4. Masahiro Fujita, Hiroaki Kitano, Koji Kageyama
    Reconfigurable Physical Agents. [Citation Graph (0, 0)][DBLP]
    Agents, 1998, pp:54-61 [Conf]
  5. Juan D. Velásquez, Masahiro Fujita, Hiroaki Kitano
    An Open Architecture of Remotion and Behavior Control of Autonomous Agents. [Citation Graph (0, 0)][DBLP]
    Agents, 1998, pp:473-474 [Conf]
  6. Sreeranga P. Rajan, Masahiro Fujita
    ATM Switch Design: Parametric High-Level Modeling and Formal Verification. [Citation Graph (0, 0)][DBLP]
    AMAST, 1997, pp:437-450 [Conf]
  7. Masahiro Fujita
    Model Checking: Its Basics and Reality (Embedded Tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:217-222 [Conf]
  8. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita
    Automatic partitioning for efficient combinatorial verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:67-72 [Conf]
  9. Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita
    Simultaneous Circuit Transformation and Routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:479-483 [Conf]
  10. Masahiro Fujita, Tasuku Nishihara, Daisuke Ando
    System LSI distributed collaborative design environment for both designers and CAD developers/engineers. [Citation Graph (0, 0)][DBLP]
    C5, 2006, pp:175-183 [Conf]
  11. Takeshi Matsumoto, Daisuke Ando, Tasuku Nishihara, Masahiro Fujita
    Development and Verification of a Collaborative Printing Environment. [Citation Graph (0, 0)][DBLP]
    C5, 2007, pp:99-108 [Conf]
  12. Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita
    Model Checking Based on Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    CAV, 1999, pp:418-430 [Conf]
  13. Masahiro Fujita
    Verification of Arithmetic Circuits by Comparing Two Similar Circuits. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:159-168 [Conf]
  14. Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka
    A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:76-85 [Conf]
  15. Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum
    Program Slicing of Hardware Description Languages. [Citation Graph (0, 0)][DBLP]
    CHARME, 1999, pp:298-312 [Conf]
  16. Masahiro Fujita
    Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths. [Citation Graph (0, 0)][DBLP]
    CHARME, 2005, pp:340-344 [Conf]
  17. Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik
    Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:2-6 [Conf]
  18. Armin Biere, Alessandro Cimatti, Edmund M. Clarke, Masahiro Fujita, Yunshan Zhu
    Symbolic Model Checking Using SAT Procedures instead of BDDs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:317-320 [Conf]
  19. Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni
    Multiple Error Diagnosis Based on Xlists. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:660-665 [Conf]
  20. Kuang-Chien Chen, Masahiro Fujita
    Efficient Sum-to-One Subsets Algorithm for Logic Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:443-448 [Conf]
  21. Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita
    A Resynthesis Approach for Network Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:458-463 [Conf]
  22. Edmund M. Clarke, Kenneth L. McMillan, Xudong Zhao, Masahiro Fujita, J. Yang
    Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:54-60 [Conf]
  23. Indradeep Ghosh, Masahiro Fujita
    Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:43-48 [Conf]
  24. Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi
    Formal verification - prove it or pitch it. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:710-711 [Conf]
  25. Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita
    Advanced Verification Techniques Based on Learning. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:420-426 [Conf]
  26. Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita
    Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:585-590 [Conf]
  27. Yuan Lu, Jawahar Jain, Edmund M. Clarke, Masahiro Fujita
    Efficient variable ordering using aBDD based sampling. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:687-692 [Conf]
  28. Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira
    Using Complementation and Resequencing to Minimize Transitions. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:694-697 [Conf]
  29. Hitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro Fujita
    Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:284-289 [Conf]
  30. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
    An Efficient Filter-Based Approach for Combinational Verification. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:132-137 [Conf]
  31. Rajeev Murgai, Masahiro Fujita
    On Reducing Transitions Through Data Modifications. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:82-0 [Conf]
  32. Edmund M. Clarke, Masahiro Fujita, David P. Gluch
    Model Checking for Dependable Software-Intensive Systems. [Citation Graph (0, 0)][DBLP]
    DSN, 2003, pp:764- [Conf]
  33. Ben Chen, Michihiro Yamazaki, Masahiro Fujita
    Bug Identification of a Real Chip Design by Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:132-136 [Conf]
  34. Masahiro Fujita, Hidehiko Tanaka, Tohru Moto-Oka
    Specifying Hardware in temporal Logic & Efficient Synthesis of State-Diagrams Using Prolog. [Citation Graph (0, 0)][DBLP]
    FGCS, 1984, pp:572-581 [Conf]
  35. Masahiro Fujita, Sreeranga P. Rajan, Alan J. Hu
    Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol. [Citation Graph (0, 0)][DBLP]
    FM-Trends, 1998, pp:281-295 [Conf]
  36. Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita
    Decomposition Techniques for Efficient ROBDD Construction. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:419-434 [Conf]
  37. Thanyapat Sakunkonchak, Masahiro Fujita
    Verification of Event-Based Synchronization of SpecC Description Using Difference Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    FORTE, 2002, pp:369- [Conf]
  38. Masahiro Fujita, Yuji Kukimoto
    Patching Method for Lookup-Table Type FPLs. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:61-70 [Conf]
  39. Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
    Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:137-144 [Conf]
  40. Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
    System level design language extensions for timed/untimed digital-analog combined system design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:130-133 [Conf]
  41. Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima
    Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies. [Citation Graph (0, 0)][DBLP]
    HICSS, 2003, pp:279- [Conf]
  42. Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita
    Speeding up technology-independent timing optimization by network partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:83-90 [Conf]
  43. Robert J. Carragher, Chung-Kuan Cheng, Masahiro Fujita
    An efficient algorithm for the net matching problem. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:640-644 [Conf]
  44. Edmund M. Clarke, Masahiro Fujita, Xudong Zhao
    Hybrid decision diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:159-163 [Conf]
  45. Masahiro Fujita, Yusuke Matsunaga
    Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:560-563 [Conf]
  46. Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda
    Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:38-41 [Conf]
  47. Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen
    Application of Boolean Unification to Combinational Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:510-513 [Conf]
  48. Jawahar Jain, William Adams, Masahiro Fujita
    Sampling schemes for computing OBDD variable orderings. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:631-638 [Conf]
  49. Yuji Kukimoto, Masahiro Fujita
    Rectification method for lookup-table type FPGA's. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:54-61 [Conf]
  50. Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton
    A redesign technique for combinational circuits based on gate reconnections. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:632-637 [Conf]
  51. Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda
    Multi-Level Logic Minimization Across Latch Boundaries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:406-409 [Conf]
  52. Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
    Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:547-554 [Conf]
  53. Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita
    LP based cell selection with constraints of timing, area, and power consumption. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:378-381 [Conf]
  54. Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng
    Simple tree-construction heuristics for the fanout problem . [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:671-679 [Conf]
  55. Kuang-Chien Chen, Masahiro Fujita
    Concurrent Resynthesis for Network Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:44-48 [Conf]
  56. Masahiro Fujita
    RTL Design Verification by Making Use of Datapath Information. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:592-597 [Conf]
  57. Masahiro Fujita, Shinji Kono
    Synthesis of Controllers from Interval Temporal Logic Specification. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:242-245 [Conf]
  58. Alan J. Hu, Masahiro Fujita, Chris Wilson
    Formal Verification of the HAL S1 System Cache Coherence Protocol. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:438-444 [Conf]
  59. Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
    A Survey of Techniques for Formal Verification of Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:445-454 [Conf]
  60. Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose
    Logic synthesis for a single large look-up table. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:415-0 [Conf]
  61. H. Sato, Michihiro Yamazaki, Masahiro Fujita
    YEPHCAD and FLORA: Logic Synthesis for Control and Datapath. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:527-530 [Conf]
  62. Gregory Hornby, Seiichi Takamura, Osamu Hanagata, Masahiro Fujita, Jordan B. Pollack
    Evolution of Controllers from a High-Level Simulator to a High DOF Robot. [Citation Graph (0, 0)][DBLP]
    ICES, 2000, pp:80-89 [Conf]
  63. Masahiro Fujita, Shinji Kono, Hidehiko Tanaka, Tohru Moto-Oka
    Tokio: Logic Programming Language Based on Temporal Logic and its Compilation to Prolog. [Citation Graph (0, 0)][DBLP]
    ICLP, 1986, pp:695-709 [Conf]
  64. Ronald C. Arkin, Masahiro Fujita, Tsuyoshi Takagi, Rika Hasegawa
    Ethological Modeling and Architecture for an Entertainment Robot. [Citation Graph (0, 0)][DBLP]
    ICRA, 2001, pp:453-458 [Conf]
  65. Masahiro Fujita
    Digital Creatures for Future Entertainment Robotics. [Citation Graph (0, 0)][DBLP]
    ICRA, 2000, pp:801-806 [Conf]
  66. Gregory Hornby, Seiichi Takamura, Jun Yokono, Osamu Hanagata, Takashi Yamamoto, Masahiro Fujita
    Evolving Robust Gaits with AIBO. [Citation Graph (0, 0)][DBLP]
    ICRA, 2000, pp:3040-3045 [Conf]
  67. Hiroaki Kitano, Masahiro Fujita, Stéphane Zrehen, Koji Kageyama
    Sony Legged Robot for RoboCup Challenge. [Citation Graph (0, 0)][DBLP]
    ICRA, 1998, pp:2605-2612 [Conf]
  68. Yoshihiro Kuroki, Masahiro Fujita, Tatsuzo Ishida, Ken'ichiro Nagasaka, Jin'ichi Yamaguchi
    A small biped entertainment robot exploring attractive applications. [Citation Graph (0, 0)][DBLP]
    ICRA, 2003, pp:471-476 [Conf]
  69. T. Sakaguchi, Masahiro Fujita, Hiroshi Watanabe, Fumio Miyazaki
    Motion Planning and Control for a Robot Performer. [Citation Graph (0, 0)][DBLP]
    ICRA (3), 1993, pp:925-931 [Conf]
  70. Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita
    Speeding Up Look-up-Table Driven Logic Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:385-397 [Conf]
  71. Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita
    Real-Time Path Planning for Humanoid Robot Navigation. [Citation Graph (0, 0)][DBLP]
    IJCAI, 2005, pp:1232-1237 [Conf]
  72. Zhen-Ping Lo, Masahiro Fujita, Behnam Bavarian
    Analysis of Neighborhood Interaction in Kohonen Neural Networks. [Citation Graph (0, 0)][DBLP]
    IPPS, 1991, pp:246-249 [Conf]
  73. Masahiro Fujita, Shunsuke Sasaki, Ken Matsui
    Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse. [Citation Graph (0, 0)][DBLP]
    IRI, 2005, pp:318-325 [Conf]
  74. Masahiro Fujita, Jerry Chih-Yuan Yang, Edmund M. Clarke, Xudong Zhao, Patrick C. McGeer
    Fast Spectrum Computation for Logic Functions using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:275-278 [Conf]
  75. Minoru Asada, Andreas Birk 0002, Enrico Pagello, Masahiro Fujita, Itsuki Noda, Satoshi Tadokoro, Dominique Duhaut, Peter Stone, Manuela M. Veloso, Tucker R. Balch, Hiroaki Kitano, Brian Thomas
    Progress in RoboCup Soccer Research in 2000. [Citation Graph (0, 0)][DBLP]
    ISER, 2000, pp:363-372 [Conf]
  76. Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita
    Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:370-375 [Conf]
  77. Masahiro Fujita, Hiroshi Nakamura
    The standard SpecC language. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:81-86 [Conf]
  78. Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
    Power analysis and low-power scheduling techniques for embedded DSP software. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:110-115 [Conf]
  79. Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda
    New design paradigms. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:94- [Conf]
  80. Vamsi Boppana, Masahiro Fujita
    Modeling the unknown! Towards model-independent fault and error diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1094-0 [Conf]
  81. Fumihide Tanaka, Kuniaki Noda, Tsutomu Sawada, Masahiro Fujita
    Associated Emotion and Its Expression in an Entertainment Robot QRIO. [Citation Graph (0, 0)][DBLP]
    ICEC, 2004, pp:499-504 [Conf]
  82. Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
    Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:103-108 [Conf]
  83. Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya
    Logic Optimization for Asynchronous SI Controllers using Transduction Method. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:245-250 [Conf]
  84. T. Aoyagi, Masahiro Fujita, Tohru Moto-Oka
    Temporal Logic Programming Language Tokio - Programming in Tokio. [Citation Graph (0, 0)][DBLP]
    LP, 1985, pp:128-137 [Conf]
  85. Masahiro Fujita, Makoto Ishisone, Hiroshi Nakamura, Hidehiko Tanaka, Tohru Moto-Oka
    Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis. [Citation Graph (0, 0)][DBLP]
    LP, 1985, pp:246-255 [Conf]
  86. Shinji Kono, T. Aoyagi, Masahiro Fujita, Hidehiko Tanaka
    Implementation of Temporal Logic Programming Language Tokio. [Citation Graph (0, 0)][DBLP]
    LP, 1985, pp:138-147 [Conf]
  87. Hiroshi Nakamura, Masaya Nakai, Shinji Kono, Masahiro Fujita, Hidehiko Tanaka
    Logic Design Assistence Using Temporal Logic Based Language Tokio. [Citation Graph (0, 0)][DBLP]
    LP, 1989, pp:174-183 [Conf]
  88. Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita
    Engineering Changes in Field Modifiable Architectures. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2003, pp:87-94 [Conf]
  89. Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
    Synchronization verification in system-level design with ILP solvers. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:121-130 [Conf]
  90. Masahiro Fujita
    Extended abstract: a formal design approach from software oriented UML descriptions to hardware oriented RTL. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:241-242 [Conf]
  91. Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada
    Comparative Study On Verilog-Based And C-Based Hardware Design Education. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:41-42 [Conf]
  92. Takashi Michikawa, Takashi Kanai, Masahiro Fujita, Hiroaki Chiyokura
    Multiresolution Interpolation Meshes. [Citation Graph (0, 0)][DBLP]
    Pacific Conference on Computer Graphics and Applications, 2001, pp:60-69 [Conf]
  93. Hiroshi Nakamura, Takanori Arai, Masahiro Fujita
    Formal Verification of a Pipelined Processor with New Memory. [Citation Graph (0, 0)][DBLP]
    PRDC, 2002, pp:321-324 [Conf]
  94. Masahiro Fujita
    Sony Four Legged Robot League at RoboCup 2002. [Citation Graph (0, 0)][DBLP]
    RoboCup, 2002, pp:469-476 [Conf]
  95. Masahiro Fujita, Hiroaki Kitano, Koji Kageyama
    A Legged Robot for RoboCup Based on "OPENR". [Citation Graph (0, 0)][DBLP]
    RoboCup, 1997, pp:168-180 [Conf]
  96. Masahiro Fujita, Stéphane Zrehen, Hiroaki Kitano
    A Quadruped Robot for RoboCup Legged Robot Challenge in Paris '98. [Citation Graph (0, 0)][DBLP]
    RoboCup, 1998, pp:125-140 [Conf]
  97. Peter Stone, Minoru Asada, Tucker R. Balch, Masahiro Fujita, Gerhard K. Kraetzschmar, Henrik Hautop Lund, Paul Scerri, Satoshi Tadokoro, Gordon Wyeth
    Overview of RoboCup-2000. [Citation Graph (0, 0)][DBLP]
    RoboCup, 2000, pp:1-28 [Conf]
  98. Manuela M. Veloso, Hiroaki Kitano, Enrico Pagello, Gerhard K. Kraetzschmar, Peter Stone, Tucker R. Balch, Minoru Asada, Silvia Coradeschi, Lars Karlsson, Masahiro Fujita
    Overview of RoboCup-99. [Citation Graph (0, 0)][DBLP]
    RoboCup, 1999, pp:1-34 [Conf]
  99. Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
    Hierarchical Error Diagnosis Targeting RTL Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:436-441 [Conf]
  100. Masahiro Fujita
    Formal Verification of C Language Based VLSI Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:93-0 [Conf]
  101. Indradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita
    High Level Design Validation: Current Practices and Future Directions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:9-11 [Conf]
  102. Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
    Formal Verification of Combinational Circuit. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:218-225 [Conf]
  103. Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra
    Sequential Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:18-19 [Conf]
  104. Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
    On More Efficient Combinational ATPG Using Functional Learning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:107-110 [Conf]
  105. Rajeev Murgai, Masahiro Fujita
    Some Recent Advances in Software and Hardware Logic Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:232-238 [Conf]
  106. Rajeev Murgai, Jawahar Jain, Masahiro Fujita
    Efficient Scheduling Techniques for ROBDD Construction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:394-401 [Conf]
  107. Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    A study of composition schemes for mixed apply/compose based construction of ROBDDs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:249-253 [Conf]
  108. Sreeranga P. Rajan, Masahiro Fujita
    Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:552-557 [Conf]
  109. Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita
    Simultaneous Circuit Transformation and Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:479-483 [Conf]
  110. Tetsuro Ogi, Toshio Yamada, Michitaka Hirose, Masahiro Fujita, Kazuto Kuzuu
    High Presence Remote Presentation in the Shared Immersive Virtual World. [Citation Graph (0, 0)][DBLP]
    VR, 2003, pp:289-290 [Conf]
  111. Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao
    Testing, Verification, and Diagnosis in the Presence of Unknowns. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:263-270 [Conf]
  112. Ankur Jain, Michael S. Hsiao, Vamsi Boppana, Masahiro Fujita
    On the Evaluation of Arbitrary Defect Coverage of Test Sets. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:426-432 [Conf]
  113. Ken Matsui, Masahiro Fujita
    Object-oriented analysis and specification for HW/SW co-design with UML diagrams. [Citation Graph (0, 0)][DBLP]
    ACST, 2006, pp:38-43 [Conf]
  114. Minoru Asada, Oliver Obst, Daniel Polani, Brett Browning, Andrea Bonarini, Masahiro Fujita, Thomas Christaller, Tomoichi Takahashi, Satoshi Tadokoro, Elizabeth Sklar, Gal A. Kaminka
    An Overview of RoboCup-2002 Fukuoka/Busan. [Citation Graph (0, 0)][DBLP]
    AI Magazine, 2003, v:24, n:2, pp:21-40 [Journal]
  115. Masahiro Fujita, Manuela M. Veloso, William T. B. Uther, Minoru Asada, Hiroaki Kitano, Vincent Hugel, Patrick Bonnin, Jean-Christophe Bouramoué, Pierre Blazevic
    Vision, Strategy, and Localization Using the Sony Robots at . [Citation Graph (0, 0)][DBLP]
    AI Magazine, 2000, v:21, n:1, pp:47-56 [Journal]
  116. Masahiro Fujita, Hiroaki Kitano
    Development of an Autonomous Quadruped Robot for Robot Entertainment. [Citation Graph (0, 0)][DBLP]
    Auton. Robots, 1998, v:5, n:1, pp:7-18 [Journal]
  117. Shunsuke Sasaki, Tasuku Nishihara, Masahiro Fujita
    Slicing-based Hardware/Software Co-design Methodology From Functional Specifications. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:159, n:, pp:265-280 [Journal]
  118. Edmund M. Clarke, Kenneth L. McMillan, Xudong Zhao, Masahiro Fujita, J. Yang
    Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:10, n:2/3, pp:137-148 [Journal]
  119. Masahiro Fujita, Patrick C. McGeer
    Introduction to the Special Issue on Multi-Terminal Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:10, n:2/3, pp:135-136 [Journal]
  120. Masahiro Fujita, Patrick C. McGeer, Jerry Chih-Yuan Yang
    Multi-Terminal Binary Decision Diagrams: An Efficient Data Structure for Matrix Representation. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:10, n:2/3, pp:149-169 [Journal]
  121. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita
    Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2002, v:21, n:1, pp:95-101 [Journal]
  122. David W. Currie, Xiushan Feng, Masahiro Fujita, Alan J. Hu, Mark Kwan, Sreeranga P. Rajan
    Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2006, v:34, n:1, pp:61-91 [Journal]
  123. Masahiro Fujita
    AIBO: Toward the Era of Digital Creatures. [Citation Graph (0, 0)][DBLP]
    I. J. Robotic Res., 2001, v:20, n:10, pp:781-794 [Journal]
  124. Masahiro Fujita, Hidehiko Tanaka, Tohru Moto-Oka
    Temporal Logic Based Hardware Description and Its Verification with Prolog. [Citation Graph (0, 0)][DBLP]
    New Generation Comput., 1983, v:1, n:2, pp:195-203 [Journal]
  125. Ronald C. Arkin, Masahiro Fujita, Tsuyoshi Takagi, Rika Hasegawa
    An ethological and emotional basis for human-robot interaction. [Citation Graph (0, 0)][DBLP]
    Robotics and Autonomous Systems, 2003, v:42, n:3-4, pp:191-201 [Journal]
  126. Masahiro Fujita, Hiroaki Kitano, Koji Kageyama
    A reconfigurable robot platform. [Citation Graph (0, 0)][DBLP]
    Robotics and Autonomous Systems, 1999, v:29, n:2-3, pp:119-132 [Journal]
  127. Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum
    Program slicing for VHDL. [Citation Graph (0, 0)][DBLP]
    STTT, 2002, v:4, n:1, pp:125-137 [Journal]
  128. Jawahar Jain, Ingo Wegener, Masahiro Fujita
    A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1289-1290 [Journal]
  129. Robert J. Carragher, Chung-Kuan Cheng, Xiao-Ming Xiong, Masahiro Fujita, Ramamohan Paturi
    Solving the net matching problem in high-performance chip design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:902-911 [Journal]
  130. Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga
    Variable ordering algorithms for ordered binary decision diagrams and their evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:6-12 [Journal]
  131. Indradeep Ghosh, Masahiro Fujita
    Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:402-415 [Journal]
  132. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
    An efficient filter-based approach for combinational verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1542-1557 [Journal]
  133. Masahiro Fujita
    Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:4, pp:610-626 [Journal]
  134. Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee
    ATM switch design by high-level modeling, formal verification and high-level synthesi. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:554-562 [Journal]
  135. Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
    Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:553-563 [Conf]
  136. Bijan Alizadeh, Masahiro Fujita
    Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:129-144 [Conf]
  137. Yosuke Bando, Takahiro Saito, Masahiro Fujita
    Hexagonal storage scheme for interleaved frame buffers and textures. [Citation Graph (0, 0)][DBLP]
    Graphics Hardware, 2005, pp:33-40 [Conf]
  138. Yukiko Hoshino, Tsuyoshi Takagi, Ugo Di Profio, Masahiro Fujita
    Behavior Description and Control using Behavior Module for Personal Robot. [Citation Graph (0, 0)][DBLP]
    ICRA, 2004, pp:4165-4171 [Conf]
  139. Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita
    A Floor and Obstacle Height Map for 3D Navigation of a Humanoid Robot. [Citation Graph (0, 0)][DBLP]
    ICRA, 2005, pp:1066-1071 [Conf]
  140. Satoshi Komatsu, Masahiro Fujita
    An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  141. Masahiro Fujita, Subash Shankar, S. Shunsuke
    Equivalence checking: a rule-based approach. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:197- [Conf]
  142. Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
    Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:121-134 [Conf]
  143. Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
    Power analysis and minimization techniques for embedded DSP software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:123-135 [Journal]

  144. Protocol Transducer Synthesis using Divide and Conquer approach. [Citation Graph (, )][DBLP]


  145. A Post-Silicon Debug Support Using High-Level Design Description. [Citation Graph (, )][DBLP]


  146. Debugging from high level down to gate level. [Citation Graph (, )][DBLP]


  147. Polynomial datapath optimization using partitioning and compensation heuristics. [Citation Graph (, )][DBLP]


  148. Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits. [Citation Graph (, )][DBLP]


  149. Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). [Citation Graph (, )][DBLP]


  150. Improved heuristics for finite word-length polynomial datapath optimization. [Citation Graph (, )][DBLP]


  151. Adaptive grasping by multi fingered hand with tactile sensor based on robust force and position control. [Citation Graph (, )][DBLP]


  152. A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams. [Citation Graph (, )][DBLP]


  153. Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences. [Citation Graph (, )][DBLP]


  154. Synthesis and formal verification of on-chip protocol transducers through decomposed specification. [Citation Graph (, )][DBLP]


  155. Rule-Based Approaches for Equivalence Checking of SpecC Programs. [Citation Graph (, )][DBLP]


  156. Arithmetic Circuits Verification without Looking for Internal Equivalences. [Citation Graph (, )][DBLP]


  157. Pipelined Microprocessors Optimization and Debugging. [Citation Graph (, )][DBLP]


  158. SDR-4X II: A Small Humanoid as an Entertainer in Home Environment. [Citation Graph (, )][DBLP]


  159. Motion control of a virtual humanoid that can perform real physical interactions with a human. [Citation Graph (, )][DBLP]


  160. AMS Extensions for Timed/Untimed System-Level Design Language. [Citation Graph (, )][DBLP]


  161. Custom Instruction Generation with High-Level Synthesis. [Citation Graph (, )][DBLP]


  162. Intelligence Dynamics: a concept and preliminary experiments for open-ended learning agents. [Citation Graph (, )][DBLP]


  163. Functional Equivalence Verification Tools in High-Level Synthesis Flows. [Citation Graph (, )][DBLP]


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