Journals in DBLP

Journal of Systems Architecture
2005, volume: 51, number: 6-7

1. Henry Selvaraj, Lech Józwiak
   Reconfigurable embedded systems: Synthesis, design and application. [Citation Graph (0, 0)][DBLP]
   Journal of Systems Architecture, 2005, v:51, n:6-7, pp:347-349 [Journal]
   
2. Sebastian Wallner
   A configurable system-on-chip architecture for embedded and real-time applications: concepts, design and realization. [Citation Graph (0, 0)][DBLP]
   Journal of Systems Architecture, 2005, v:51, n:6-7, pp:350-367 [Journal]
   
3. Sung Woo Chung, Hyong-Shik Kim, Chu Shik Jhon
   Distance-aware L2 cache organizations for scalable multiprocessor systems. [Citation Graph (0, 0)][DBLP]
   Journal of Systems Architecture, 2005, v:51, n:6-7, pp:368-381 [Journal]
   
4. Venkatesan Muthukumar, Bharath Radhakrishnan, Henry Selvaraj
   Multiple voltage and frequency scheduling for power minimization. [Citation Graph (0, 0)][DBLP]
   Journal of Systems Architecture, 2005, v:51, n:6-7, pp:382-394 [Journal]
   
5. Syed Saif Abrar
   Novel source-independent characterization methodology for embedded software energy estimation and optimization. [Citation Graph (0, 0)][DBLP]
   Journal of Systems Architecture, 2005, v:51, n:6-7, pp:395-404 [Journal]
   
6. Lech Józwiak, Szymon Bieganski, Artur Chojnacki
   Information-driven circuit synthesis with the pre-characterized gate libraries. [Citation Graph (0, 0)][DBLP]
   Journal of Systems Architecture, 2005, v:51, n:6-7, pp:405-423 [Journal]
   
7. Mariusz Rawski, Henry Selvaraj, Tadeusz Luba
   An application of functional decomposition in ROM-based FSM implementation in FPGA devices. [Citation Graph (0, 0)][DBLP]
   Journal of Systems Architecture, 2005, v:51, n:6-7, pp:424-434 [Journal]
   
8. S. Ramachandran, S. Srinivasan
   Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization. [Citation Graph (0, 0)][DBLP]
   Journal of Systems Architecture, 2005, v:51, n:6-7, pp:435-450 [Journal]