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Sung Woo Chung :
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Sung Woo Chung , Sung-Bae Park A Low Power Branch Predictor to Selectively Access the BTB. [Citation Graph (0, 0)][DBLP ] Asia-Pacific Computer Systems Architecture Conference, 2004, pp:374-384 [Conf ] Sung Woo Chung , Kevin Skadron Using Branch Prediction Information for Near-Optimal I-Cache Leakage. [Citation Graph (0, 0)][DBLP ] Asia-Pacific Computer Systems Architecture Conference, 2006, pp:24-37 [Conf ] Soong Hyun Shin , Sung Woo Chung , Chu Shik Jhon On the Reliability of Drowsy Instruction Caches. [Citation Graph (0, 0)][DBLP ] Asia-Pacific Computer Systems Architecture Conference, 2006, pp:445-451 [Conf ] Sung Woo Chung , Seong Tae Jhang , Chu Shik Jhon Analysis of slotted ring network in real-time systems. [Citation Graph (0, 0)][DBLP ] Computers and Their Applications, 2000, pp:5-8 [Conf ] Yongsoo Joo , Yongseok Choi , Chanik Park , Sung Woo Chung , EuiYoung Chung , Naehyuck Chang Demand paging for OneNANDTM Flash eXecute-in-place. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2006, pp:229-234 [Conf ] Sung Woo Chung , Hyong-Shik Kim , Chu Shik Jhon Distance-aware L2 Cache Organizations for Scalable Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] DSD, 2003, pp:24-32 [Conf ] Hyo-Joong Suh , Sung Woo Chung An Accurate Architectural Simulator for ARM1136. [Citation Graph (0, 0)][DBLP ] EUC, 2005, pp:331-339 [Conf ] Gi-Ho Park , Sung Woo Chung , Han-Jong Kim , Jung-Bin Im , Jung-Wook Park , Shin-Dug Kim , Sung-Bae Park Practice and Experience of an Embedded Processor Core Modeling. [Citation Graph (0, 0)][DBLP ] HPCC, 2006, pp:621-630 [Conf ] Sung Woo Chung , Seong Tae Jhang , Chu Shik Jhon PANDA: Ring-Based Multiprocessor System Using New Snooping Protocol. [Citation Graph (0, 0)][DBLP ] ICPADS, 1998, pp:10-17 [Conf ] Sung Woo Chung , Hyong-Shik Kim , Chu Shik Jhon Accelerating the Continuous Data in a SCI-Based Multimedia System. [Citation Graph (0, 0)][DBLP ] ICPADS, 2001, pp:171-178 [Conf ] Sung Woo Chung , Kevin Skadron A Novel Software Solution for Localized Thermal Problems. [Citation Graph (0, 0)][DBLP ] ISPA, 2006, pp:63-74 [Conf ] Sung Woo Chung , Chu Shik Jhon , Hyong-Shik Kim An Effective L2 Cache Replacement Policy to Distribute the Bus Traffic in the SMP Node. [Citation Graph (0, 0)][DBLP ] IASTED PDCS, 2002, pp:782-787 [Conf ] Sung Woo Chung , Chu Shik Jhon Optimal Interconnection Network Bandwidth for Ring-Based Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] PDPTA, 1999, pp:2266-2271 [Conf ] Byoung Soon Jang , Sung Woo Chung , Seong Tae Jhang , Chu Shik Jhon Efficient schemes to scale the interconnection network bandwidth in a ring-based multiprocessor system. [Citation Graph (0, 0)][DBLP ] SAC, 2001, pp:510-516 [Conf ] Cheol Hong Kim , Sung-Hoon Shim , Jong Wook Kwak , Sung Woo Chung , Chu Shik Jhon First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption. [Citation Graph (0, 0)][DBLP ] SAMOS, 2005, pp:103-111 [Conf ] Sung Woo Chung , Hyong-Shik Kim , Chu Shik Jhon A Split L2 Data Cache for Scalable Cc-numa Multiprocessors. [Citation Graph (0, 0)][DBLP ] Journal of Circuits, Systems, and Computers, 2005, v:14, n:3, pp:605-618 [Journal ] Sung Woo Chung , Jeong-Heon Shin , Hyong-Shik Kim , Chu Shik Jhon A Second-Level Cache With the Distance-Aware Replacement Policy for NUMA Systems. [Citation Graph (0, 0)][DBLP ] J. Inf. Sci. Eng., 2002, v:18, n:5, pp:803-813 [Journal ] Sung Woo Chung , Hyong-Shik Kim , Chu Shik Jhon Distance-aware L2 cache organizations for scalable multiprocessor systems. [Citation Graph (0, 0)][DBLP ] Journal of Systems Architecture, 2005, v:51, n:6-7, pp:368-381 [Journal ] Hyo-Joong Suh , Sung Woo Chung DRACO: optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latency. [Citation Graph (0, 0)][DBLP ] SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:10-16 [Journal ] Cheol Hong Kim , Sung Woo Chung , Chu Shik Jhon PP-cache: A partitioned power-aware instruction cache architecture. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2006, v:30, n:5, pp:268-279 [Journal ] Sung Woo Chung , Gi-Ho Park , Hyo-Joong Suh , Han-Jong Kim , Jung-Bin Im , Jung-Wook Park , Sung-Bae Park Sim-ARM1136: A case study on the accuracy of the cycle-accurate simulator. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2006, v:30, n:3, pp:137-144 [Journal ] Is the Complicated ECC Array Necessary for Data Caches? [Citation Graph (, )][DBLP ] Selective wordline voltage boosting for caches to manage yield under process variations. [Citation Graph (, )][DBLP ] Exploiting narrow-width values for thermal-aware register file designs. [Citation Graph (, )][DBLP ] An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching. [Citation Graph (, )][DBLP ] Energy-optimal dynamic thermal management for green computing. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.328secs