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Publications of Author

1. Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
   Floorplan driven leakage power aware IP-based SoC design space exploration. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2006, pp:118-123 [Conf]
   
2. P. Garg, Aseem Gupta, Jerzy W. Rozenblit
   Performance Analysis of Embedded Systems in the Virtual Component Co-Design Environment. [Citation Graph (0, 0)][DBLP]
   ECBS, 2004, pp:61-68 [Conf]
   
3. Claudio Talarico, Aseem Gupta, Ebenezer Peter, Jerzy W. Rozenblit
   Embedded System Engineering Using C/C₊₊ Based Design Methodologies. [Citation Graph (0, 0)][DBLP]
   ECBS, 2005, pp:81-88 [Conf]
   
4. Brian Kahne, Aseem Gupta, Peter Wilson, Nikil D. Dutt
   An Introduction to the Plasma Language. [Citation Graph (0, 0)][DBLP]
   MTV, 2005, pp:12-22 [Conf]
   
5. Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
   STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2007, pp:559-564 [Conf]
   
6. 
   LEAF: A System Level Leakage-Aware Floorplanner for SoCs. [Citation Graph (, )][DBLP]
   
   
7. 
   Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. [Citation Graph (, )][DBLP]
   
   
8. 
   TRAM: A tool for Temperature and Reliability Aware Memory Design. [Citation Graph (, )][DBLP]
   
   
9. 
   RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor. [Citation Graph (, )][DBLP]
   
   
10. 
    Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. [Citation Graph (, )][DBLP]
    
    
11. 
    PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors. [Citation Graph (, )][DBLP]