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Fadi J. Kurdahi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kang Yi, Kyeong-Hoon Jung, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil
    Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:295-308 [Conf]
  2. Chunhui Zhang, Fadi J. Kurdahi
    On combining iteration space tiling with data space tiling for scratch-pad memory systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:973-976 [Conf]
  3. Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm
    A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:116-125 [Conf]
  4. Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi
    A constraint-based application model and scheduling techniques for power-aware systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:153-158 [Conf]
  5. Behzad Mohebbi, Eliseu Chavez Filho, Rafael Maestre, Mark Davies, Fadi J. Kurdahi
    A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:103-108 [Conf]
  6. Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
    Floorplan driven leakage power aware IP-based SoC design space exploration. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:118-123 [Conf]
  7. Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt
    System-level power-performance trade-offs in bus matrix communication architecture synthesis. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:300-305 [Conf]
  8. Fadi J. Kurdahi, Alice C. Parker
    PLEST: a program for area estimation of VLSI integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:467-473 [Conf]
  9. Fadi J. Kurdahi, Alice C. Parker
    REAL: a program for REgister ALlocation. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:210-215 [Conf]
  10. Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi
    Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:840-845 [Conf]
  11. D. Sreenivasa Rao, Fadi J. Kurdahi
    Partitioning by Regularity Extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:235-238 [Conf]
  12. Hartej Singh, Guangming Lu, Eliseu M. Chaves Filho, Rafael Maestre, Ming-Hau Lee, Fadi J. Kurdahi, Nader Bagherzadeh
    MorphoSys: case study of a reconfigurable computing system targeting multimedia applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:573-578 [Conf]
  13. Min Xu, Fadi J. Kurdahi
    Layout-Driven High Level Synthesis for FPGA Based Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:446-450 [Conf]
  14. Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh, Román Hermida, Milagros Fernández
    Kernel Scheduling in Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:90-96 [Conf]
  15. Marcos Sanchez-Elez, Milagros Fernández, Rafael Maestre, Fadi J. Kurdahi, Román Hermida, Nader Bagherzadeh
    A Complete Data Scheduler for Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:547-552 [Conf]
  16. Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves
    The MorphoSys Dynamically Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 1999, pp:152-160 [Conf]
  17. Champaka Ramachandran, Fadi J. Kurdahi
    Incorporating the Controller Effects During Register Transfer Level Synthesis. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:308-313 [Conf]
  18. Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho
    The MorphoSys Parallel Reconfigurable System. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:727-734 [Conf]
  19. Hooman Parizi, Afshin Niktash, Nader Bagherzadeh, Fadi J. Kurdahi
    MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2002, pp:844-848 [Conf]
  20. Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi
    Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:239-0 [Conf]
  21. Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh
    Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:297-298 [Conf]
  22. Douglas M. Blough, Fadi J. Kurdahi, Seong Yong Ohm
    Optimal Recovery Point Insertion for High-Level Synthesis of Recoverable Microarchitectures. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:50-59 [Conf]
  23. Dirk Stroobandt, Fadi J. Kurdahi
    On the Characterization of Multi-Point Nets in Electronic Designs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:344-0 [Conf]
  24. James J. Kim, Fadi J. Kurdahi, Nohbyung Park
    Automatic Synthesis of Time-Stationary Controllers for Pipelined Data Paths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:30-33 [Conf]
  25. Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt
    Comprehensive lower bound estimation from behavioral descriptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:182-187 [Conf]
  26. Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul
    Accurate layout area and delay modeling for system level design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:355-361 [Conf]
  27. Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh
    Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:575-576 [Conf]
  28. Guangming Lu, Ming-Hau Lee, Hartej Singh, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho
    MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:661-669 [Conf]
  29. Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida N. Kanj, Sani R. Nassif
    System-Level SRAM Yield Enhancement. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:179-184 [Conf]
  30. Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi, Rouwaida Kanj
    Cross Layer Error Exploitation for Aggressive Voltage Scaling. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:192-197 [Conf]
  31. Min Xu, Fadi J. Kurdahi
    Layout-Driven RTL Binding Techniques for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:33-38 [Conf]
  32. Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Nader Bagherzadeh, Hartej Singh
    Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:107-114 [Conf]
  33. Seong Yong Ohm, Fadi J. Kurdahi, Nikil Dutt, Min Xu
    A comprehensive estimation technique for high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:122-127 [Conf]
  34. Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh
    A data scheduler for multi-context reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:177-182 [Conf]
  35. Chunhui Zhang, Yun Long, Fadi J. Kurdahi
    A Scalable Embedded JPEG2000 Architecture. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:334-343 [Conf]
  36. Pradip K. Jha, Champaka Ramachandran, Nikil D. Dutt, Fadi J. Kurdahi
    An Empirical Study on the Effects of Physical Design in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:11-16 [Conf]
  37. A. Sriram, Fadi J. Kurdahi
    Behavioral Modeling of an ATM Switch using SpecCharts. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:19-22 [Conf]
  38. Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
    STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:559-564 [Conf]
  39. Fadi J. Kurdahi, Nader Bagherzadeh, Peter Athanas, Jose L. Muñoz
    Guest Editors' Introduction: Configurable Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:1, pp:17-19 [Journal]
  40. Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh, Eliseu M. Chaves Filho
    MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:5, pp:465-481 [Journal]
  41. Douglas M. Blough, Fadi J. Kurdahi, Seong Yong Ohm
    Optimal algorithms for recovery point insertion in recoverable microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:945-955 [Journal]
  42. Lars W. Hagen, Andrew B. Kahng, Fadi J. Kurdahi, Champaka Ramachandran
    On the intrinsic Rent parameter and spectra-based partitioning methodologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:27-37 [Journal]
  43. Fadi J. Kurdahi, Alice C. Parker
    Techniques for area estimation of VLSI layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:81-92 [Journal]
  44. Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt
    A unified lower bound estimation technique for high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:458-472 [Journal]
  45. Champaka Ramachandran, Fadi J. Kurdahi
    Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1450-1460 [Journal]
  46. D. Sreenivasa Rao, Fadi J. Kurdahi
    On clustering for maximal regularity extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1198-1208 [Journal]
  47. Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm, Jeffrey Hammes
    Automatic compilation to a coarse-grained reconfigurable system-opn-chip. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:4, pp:560-589 [Journal]
  48. Min Xu, Fadi J. Kurdahi
    Layout-driven RTL binding techniques for high-level synthesis using accurate estimators. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:4, pp:312-343 [Journal]
  49. Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi
    Compile-time area estimation for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:104-122 [Journal]
  50. Kang Yi, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil
    An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:102-113 [Conf]
  51. Chunhui Zhang, Fadi J. Kurdahi
    Reducing Off-Chip Memory Access via Stream-Conscious Tiling on Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2007, v:35, n:1, pp:63-98 [Journal]
  52. Chunhui Zhang, Yun Long, Fadi J. Kurdahi
    A scalable embedded JPEG 2000 architecture. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:8, pp:524-538 [Journal]
  53. Min Xu, Fadi J. Kurdahi
    Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:4, pp:411-418 [Journal]
  54. Fadi J. Kurdahi, Champaka Ramachandran
    Evaluating layout area tradeoffs for high level applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:46-55 [Journal]
  55. D. Sreenivasa Rao, Fadi J. Kurdahi
    Hierarchical design space exploration for a class of digital systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:282-295 [Journal]
  56. Douglas M. Blough, Fadi J. Kurdahi, Seong Yong Ohm
    High-level synthesis of recoverable VLSI microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:4, pp:401-410 [Journal]
  57. Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh
    A framework for reconfigurable computing: task scheduling and context management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:858-873 [Journal]
  58. Fadi J. Kurdahi
    Guest editorial special issue on system synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:377-378 [Journal]

  59. LEAF: A System Level Leakage-Aware Floorplanner for SoCs. [Citation Graph (, )][DBLP]


  60. Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications. [Citation Graph (, )][DBLP]


  61. A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache). [Citation Graph (, )][DBLP]


  62. Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. [Citation Graph (, )][DBLP]


  63. Methodology for multi-granularity embedded processor power model generation for an ESL design flow. [Citation Graph (, )][DBLP]


  64. RTL synthesis with physical and controller information. [Citation Graph (, )][DBLP]


  65. Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling. [Citation Graph (, )][DBLP]


  66. TRAM: A tool for Temperature and Reliability Aware Memory Design. [Citation Graph (, )][DBLP]


  67. Error-Aware Design. [Citation Graph (, )][DBLP]


  68. Cross-layer co-exploration of exploiting error resilience for video over wireless applications. [Citation Graph (, )][DBLP]


  69. Size-Reconfiguration Delay Tradeoffs for a Class of DSP Blocks in Multi-mode Communication Systems. [Citation Graph (, )][DBLP]


  70. RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor. [Citation Graph (, )][DBLP]


  71. Limits on voltage scaling for caches utilizing fault tolerant techniques. [Citation Graph (, )][DBLP]


  72. System level power estimation methodology with H.264 decoder prediction IP case study. [Citation Graph (, )][DBLP]


  73. Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. [Citation Graph (, )][DBLP]


  74. Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks. [Citation Graph (, )][DBLP]


  75. Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices. [Citation Graph (, )][DBLP]


  76. PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors. [Citation Graph (, )][DBLP]


  77. Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips. [Citation Graph (, )][DBLP]


  78. Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures. [Citation Graph (, )][DBLP]


  79. Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications. [Citation Graph (, )][DBLP]


  80. Fault Tolerant Approaches Targeting Ultra Low Power Communications System Design. [Citation Graph (, )][DBLP]


  81. Power Management for Cognitive Radio Platforms. [Citation Graph (, )][DBLP]


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