The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Hemanth Sampath: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
    Fast and accurate parasitic capacitance models for layout-aware. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:145-150 [Conf]
  2. Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
    Accurate Estimation of Parasitic Capacitances in Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1364-1365 [Conf]
  3. Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen
    Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:604-609 [Conf]
  4. Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri
    A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:271-276 [Conf]
  5. Hemanth Sampath, Ranga Vemuri
    MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:416-421 [Conf]

  6. Field Results on MIMO Performance in UMB Systems. [Citation Graph (, )][DBLP]


Search in 0.001secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002