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Publications of Author

1. Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana
   High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:1090- [Conf]
   
2. Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin
   GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:299-304 [Conf]
   
3. Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin
   Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2001, pp:313-324 [Conf]
   
4. Laurent Fesquet, Jerome Quartana, Marc Renaudin
   Asynchronous Systems on Programmable Logic. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2005, pp:105-112 [Conf]
   
5. Pascal Manet, Jean-Baptiste Rigaud, Julien Francq, Marc Jeambrun, Assia Tria, Bruno Robisson, Jerome Quartana, Selma Laabidi
   Integrated Evaluation Platform for Secured Devices. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2006, pp:214-219 [Conf]
   
6. Jerome Quartana, Laurent Fesquet, Marc Renaudin
   Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2005, pp:195-207 [Conf]