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Laurent Fesquet: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wissam Hlayhel, Daniel Litaize, Laurent Fesquet, Jacques Collet
    Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:22-29 [Conf]
  2. F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin
    Asynchronous FIR Filters: Towards a New Digital Processing Chain. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:198-206 [Conf]
  3. Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin
    A New Class of Asynchronous A/D Converters Based on Time Quantization. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:196-205 [Conf]
  4. N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin
    FPGA Architecture for Multi-Style Asynchronous Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:32-33 [Conf]
  5. Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana
    High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1090- [Conf]
  6. Wissam Hlayhel, Jacques Collet, Laurent Fesquet
    Implementing Snoop-Coherence Protocol for Future SMP Architectures. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:745-752 [Conf]
  7. Laurent Fesquet, Marc Renaudin
    A Programmable Logic Architecture for Prototyping Clockless Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:293-298 [Conf]
  8. Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland
    Implementing Asynchronous Circuits on LUT Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:36-46 [Conf]
  9. Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin
    GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:299-304 [Conf]
  10. Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin
    Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:313-324 [Conf]
  11. Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin
    Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:191-196 [Conf]
  12. Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard
    Low-Power Asynchronous A/D Conversion. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:81-91 [Conf]
  13. Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin
    Dynamic Voltage Scheduling for Real Time Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:390-399 [Conf]
  14. Laurent Fesquet, Jerome Quartana, Marc Renaudin
    Asynchronous Systems on Programmable Logic. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:105-112 [Conf]
  15. Katell Morin-Allory, Laurent Fesquet, Dominique Borrione
    Asynchronous Assertion Monitors for multi-Clock Domain System Verification. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2006, pp:98-102 [Conf]
  16. Philippe Hoogvorst, Sylvain Guilley, Sumanta Chau, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet
    A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:15-22 [Conf]
  17. Jerome Quartana, Laurent Fesquet, Marc Renaudin
    Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:195-207 [Conf]
  18. Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin
    State-holding in Look-Up Tables: application to asynchronous logic. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:12-17 [Conf]
  19. Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin
    Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:55-69 [Conf]
  20. N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin
    FPGA Architecture for Multi-Style Asynchronous Logic [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  21. Physical Design of FPGA Interconnect to Prevent Information Leakage. [Citation Graph (, )][DBLP]


  22. Asynchronous online-monitoring of logical and temporal assertions. [Citation Graph (, )][DBLP]


  23. PSL-based online monitoring of digital systems. [Citation Graph (, )][DBLP]


  24. A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks [Citation Graph (, )][DBLP]


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