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Publications of Author

1. Gilson I. Wirth, Michele G. Vieira, Egas Henes Neto, Fernanda Gusmão de Lima Kastensmidt
   Generation and Propagation of Single Event Transients in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
   DDECS, 2006, pp:198-203 [Conf]
   
2. Lucas Brusamarello, Roberto da Silva, Ricardo A. L. Reis, Gilson I. Wirth
   Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2007, pp:86-91 [Conf]
   
3. Egas Henes Neto, Ivandro Ribeiro, Michele G. Vieira, Gilson I. Wirth, Fernanda Lima Kastensmidt
   Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic. [Citation Graph (0, 0)][DBLP]
   SBCCI, 2005, pp:62-67 [Conf]
   
4. Gilson I. Wirth, Ivandro Ribeiro, Michele G. Vieira, Fernanda Gusmão de Lima Kastensmidt
   Single event transients in dynamic logic. [Citation Graph (0, 0)][DBLP]
   SBCCI, 2006, pp:184-189 [Conf]
   
5. Gilson I. Wirth, Michele G. Vieira, Egas Henes Neto, Fernanda Gusmão de Lima Kastensmidt
   Single event transients in combinatorial circuits. [Citation Graph (0, 0)][DBLP]
   SBCCI, 2005, pp:121-126 [Conf]
   
6. Egas Henes Neto, Ivandro Ribeiro, Michele G. Vieira, Gilson I. Wirth, Fernanda Lima Kastensmidt
   Using Bulk Built-in Current Sensors to Detect Soft Errors. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2006, v:26, n:5, pp:10-18 [Journal]
   
7. 
   "The flipped voltage follower"-based low voltage fully differential CMOS sample-and-hold circuit. [Citation Graph (, )][DBLP]
   
   
8. 
   Device degradation and resilient computing. [Citation Graph (, )][DBLP]
   
   
9. 
   Trim range limited by noise in bandgap voltage references. [Citation Graph (, )][DBLP]
   
   
10. 
    A built-in current sensor for high speed soft errors detection robust to process and temperature variations. [Citation Graph (, )][DBLP]
    
    
11. 
    Protecting digital circuits against hold time violation due to process variability. [Citation Graph (, )][DBLP]
    
    
12. 
    Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level. [Citation Graph (, )][DBLP]
    
    
13. 
    Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies. [Citation Graph (, )][DBLP]