Search the dblp DataBase

Publications of Author

1. Ricardo Reis, Fernanda Lima Kastensmidt, José Luís Almada Güntzel
   Physical design methodologies for performance predictability and manufacturability. [Citation Graph (0, 0)][DBLP]
   Conf. Computing Frontiers, 2004, pp:390-397 [Conf]
   
2. Fernanda Lima Kastensmidt, Gustavo Neuberger, Luigi Carro, Ricardo Reis
   Designing and testing fault-tolerant techniques for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
   Conf. Computing Frontiers, 2004, pp:419-432 [Conf]
   
3. Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda
   On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:1290-1295 [Conf]
   
4. Arthur Pereira Frantz, Luigi Carro, Érika F. Cota, Fernanda Lima Kastensmidt
   Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2006, pp:191-192 [Conf]
   
5. Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis
   Design of a Robust 8-Bit Microprocessor to Soft Errors. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2006, pp:195-196 [Conf]
   
6. Maico Cassel, Fernanda Lima Kastensmidt
   Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2006, pp:139-144 [Conf]
   
7. Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell
   Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2007, pp:192-197 [Conf]
   
8. Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis
   Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2005, pp:59-68 [Conf]
   
9. Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis
   Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates. [Citation Graph (0, 0)][DBLP]
   SBCCI, 2006, pp:196-201 [Conf]
   
10. Egas Henes Neto, Ivandro Ribeiro, Michele G. Vieira, Gilson I. Wirth, Fernanda Lima Kastensmidt
    Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:62-67 [Conf]
    
11. Arthur Pereira Frantz, Fernanda Lima Kastensmidt, Luigi Carro, Érika F. Cota
    Evaluation of SEU and crosstalk effects in network-on-chip switches. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:202-207 [Conf]
    
12. Fernanda Lima Kastensmidt, Gustavo Neuberger, Renato Fernandes Hentschke, Luigi Carro, Ricardo Reis
    Designing Fault-Tolerant Techniques for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:552-562 [Journal]
    
13. Egas Henes Neto, Ivandro Ribeiro, Michele G. Vieira, Gilson I. Wirth, Fernanda Lima Kastensmidt
    Using Bulk Built-in Current Sensors to Detect Soft Errors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:5, pp:10-18 [Journal]
    
14. Fernanda Lima Kastensmidt, Gustavo Neuberger, Luigi Carro, Ricardo Reis
    Desenvolvimento de Técnicas de Tolerância à Falhas para Componentes Programáveis por SRAM. [Citation Graph (0, 0)][DBLP]
    RITA, 2005, v:12, n:1, pp:47-60 [Journal]
    
15. Henrique C. Freitas, Dalton M. Colombo, Fernanda Lima Kastensmidt, Philippe Olivier Alexandre Navaux
    Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3776-3779 [Conf]
    
16. Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda
    On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
17. Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro
    Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:1, pp:47-54 [Journal]
    
18. 
    A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs. [Citation Graph (, )][DBLP]
    
    
19. 
    Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults. [Citation Graph (, )][DBLP]
    
    
20. 
    Comparing transient-fault effects on synchronous and on asynchronous circuits. [Citation Graph (, )][DBLP]
    
    
21. 
    Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs. [Citation Graph (, )][DBLP]
    
    
22. 
    Using majority logic to cope with long duration transient faults. [Citation Graph (, )][DBLP]
    
    
23. 
    A built-in current sensor for high speed soft errors detection robust to process and temperature variations. [Citation Graph (, )][DBLP]
    
    
24. 
    Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications. [Citation Graph (, )][DBLP]
    
    
25. 
    Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router. [Citation Graph (, )][DBLP]
    
    
26. 
    Evaluating memory sharing data size and TCP connections in the performance of a reconfigurable hardware-based architecture for TCP/IP stack. [Citation Graph (, )][DBLP]
    
    
27. 
    The Need for Reconfigurable Routers in Networks-on-Chip. [Citation Graph (, )][DBLP]
    
    
28. 
    Diagnosis of interconnect shorts in mesh NoCs. [Citation Graph (, )][DBLP]
    
    
29. 
    Crosstalk- and SEU-Aware Networks on Chips. [Citation Graph (, )][DBLP]