Conferences in DBLP
(sbcci) Luca Benini Advanced power management of SoC platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Paul L. Jespers A design methodology for analogue CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] John Sanguinetti The process of higher level design. [Citation Graph (0, 0)][DBLP ] Conf ] Abdelkarim Mercha Technology and architecture for deep submicron RF CMOS technology. [Citation Graph (0, 0)][DBLP ] Conf ] John Sanguinetti High level design: the future is now. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini Energy efficient NoC design. [Citation Graph (0, 0)][DBLP ] Conf ] Paul L. Jespers A survey of multistep A to D converters and error correction mechanisms. [Citation Graph (0, 0)][DBLP ] Conf ] Armando G. da Silva Jr. IC design requirements for automotive applications. [Citation Graph (0, 0)][DBLP ] Conf ] Armando Gomes , Edevaldo Pereira S. Júnior , Ivan Nascimento EMC-EMI optimized high speed CAN line driver. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Arnaud , Rafaella Fiorelli , Carlos Galup-Montoro On the design of very small transconductance OTAs with reduced input offset. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Girardi , Fernando da Rocha Paixão Cortes , Eduardo Conrad Jr. , Sergio Bampi T-shaped association of transistors: modeling of multiple channel lengths and regular associations. [Citation Graph (0, 0)][DBLP ] Conf ] E. P. Santana , N. R. Ferreira , C. E. T. Dorea , Ana Isabela Araújo Cunha On the adequate transistor modeling for optimal design of CMOS OTA. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Galup-Montoro , Márcio C. Schneider , Viriato C. Pahim Fundamentals of next generation compact MOSFET models. [Citation Graph (0, 0)][DBLP ] Conf ] Renato Fernandes Hentschke , Jagannathan Narasimhan , David Kung Improving run times by pruned application of synthesis transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolay Rubanov An efficient subcircuit recognition using the nonlinear graph matching. [Citation Graph (0, 0)][DBLP ] Conf ] Bastian Knerr , Martin Holzer 0002 , Markus Rupp Task sheduling for power optimisation of multi frequency synchronous data flow graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Duarte Lopes de Oliveira , Marius Strum , Wang Jiang Chau Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Egas Henes Neto , Ivandro Ribeiro , Michele G. Vieira , Gilson I. Wirth , Fernanda Lima Kastensmidt Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic. [Citation Graph (0, 0)][DBLP ] Conf ] Marcelo Moraes , Érika F. Cota , Luigi Carro , Flávio Rech Wagner , Marcelo Lubaszewski A constraint-based solution for on-line testing of processors embedded in real-time applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ernesto Sánchez , Matteo Sonza Reorda , Giovanni Squillero , Massimo Violante Automatic generation of test sets for SBST of microprocessor IP cores. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Arthur Lang Lisbôa , Erik Schüler , Luigi Carro Going beyond TMR for protection against multiple faults. [Citation Graph (0, 0)][DBLP ] Conf ] Xiangrong Zhou , Peter Petrov Arithmetic-based address translation for energy-efficient virtual memory support in low-power, real-time embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio Carlos Schneider Beck , Victor F. Gomes , Luigi Carro Exploiting Java through binary translation for low power embedded reconfigurable systems. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo Tavares , Paulo Romero Martins Maciel , Arthur Bessa , Raimundo S. Barreto , Leonardo Barros , Meuse N. Oliveira Jr. , Ricardo Massa Ferreira Lima A time petri net based approach for embedded hard real-time software synthesis with multiple operational modes. [Citation Graph (0, 0)][DBLP ] Conf ] Júlio C. B. de Mattos , Emilena Specht , Bruno Neves , Luigi Carro Making object oriented efficient for embedded system applications. [Citation Graph (0, 0)][DBLP ] Conf ] Richard E. Billo , Rodolfo Azevedo , Guido Araujo , Paulo Centoducatte , Eduardo Wanderley Netto Design of a decompressor engine on a SPARC processor. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Mesquita , Jean-Denis Techer , Lionel Torres , Gilles Sassatelli , Gaston Cambon , Michel Robert , Fernando Moraes Current mask generation: a transistor level security against DPA attacks. [Citation Graph (0, 0)][DBLP ] Conf ] Gilson I. Wirth , Michele G. Vieira , Egas Henes Neto , Fernanda Gusmão de Lima Kastensmidt Single event transients in combinatorial circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Leonardo Barboni , Rafaella Fiorelli Design and power optimization of CMOS RF blocks operating in the moderate inversion region. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Moreira , Eric Kerherve , P. Jarry , Didier Belot Dual-standard BiCMOS LNA for DCS1800/W-CDMA applications. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Moreira , A. A. Shirakawa , Eric Kerherve , J. M. Pham , P. Jarry , Didier Belot , P. Ancey Design of a fully-integrated BiCMOS/FBAR reconfigurable RF receiver front-end. [Citation Graph (0, 0)][DBLP ] Conf ] Angel M. Gómez Argüello , João Navarro Jr. , Wilhelmus A. M. Van Noije A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. [Citation Graph (0, 0)][DBLP ] Conf ] Sergio Gagliolo , Giacomo Pruzzo , Daniele D. Caviglia Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Sill , Frank Grassert , Dirk Timmermann Total leakage power optimization with improved mixed gates. [Citation Graph (0, 0)][DBLP ] Conf ] Shugang Wei Number conversions between RNS and mixed-radix number system based on Modulo (2p - 1 ) signed-digit arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Mariano Aguirre , Monico Linares An alternative logic approach to implement high-speed low-power full adder cells. [Citation Graph (0, 0)][DBLP ] Conf ] M. Fonseca , Eduardo A. C. da Costa , Sergio Bampi , José C. Monteiro Design of a radix-2m hybrid array multiplier using carry save adder format. [Citation Graph (0, 0)][DBLP ] Conf ] Aline Mello , Leonel Tedesco , Ney Calazans , Fernando Moraes Virtual channels in networks on chip: implementation and evaluation on hermes NoC. [Citation Graph (0, 0)][DBLP ] Conf ] Leonel Tedesco , Aline Mello , Diego Garibotti , Ney Calazans , Fernando Moraes Traffic generation and performance evaluation for mesh-based NoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Márcio Eduardo Kreutz , César A. M. Marcon , Luigi Carro , Flávio Rech Wagner , Altamiro Amadeu Susin Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures. [Citation Graph (0, 0)][DBLP ] Conf ] José Carlos S. Palma , César A. M. Marcon , Fernando Gehm Moraes , Ney Laert Vilar Calazans , Ricardo A. L. Reis , Altamiro Amadeu Susin Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Conrado Rossi , Pablo Aguirre Ultra-low power CMOS cells for temperature sensors. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Dualibe , Pablo Petrashin , Luis Toledo , Walter Lancioni New low-voltage electrically tunable triode-MOSFET transconductor and its application to low-frequency Gm-C filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Arnaud An efficient chopper amplifier, using a switched Gm-C Filter technique. [Citation Graph (0, 0)][DBLP ] Conf ] Jung Hyun Choi Minimization of parasitic effects on the design of an accurate 2-MHz RC oscillator for low voltage and low power applications. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio Pullini , Federico Angiolini , Davide Bertozzi , Luca Benini Fault tolerance overhead in network-on-chip flow control schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Sujan Pandey , Manfred Glesner , Max Mühlhäuser Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Florian Dittmann , Markus Heberling Placement of intermodule connections on partially reconfigurable devices. [Citation Graph (0, 0)][DBLP ] Conf ] Elvio Dutra , Leandro Soares Indrusiak , Manfred Glesner Non-linear addressing scheme for a lookup-based transformation function in a reconfigurable noise generator. [Citation Graph (0, 0)][DBLP ] Conf ] David Varghese , J. N. Ross A continuous-time hierarchical field programmable analogue array for rapid prototyping and hierarchical approach to analogue systems design. [Citation Graph (0, 0)][DBLP ] Conf ] 