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Publications of Author

1. John Sachs Beeckler, Warren J. Gross
   FPGA Particle Graphics Hardware. [Citation Graph (0, 0)][DBLP]
   FCCM, 2005, pp:85-94 [Conf]
   
2. Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak
   An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding. [Citation Graph (0, 0)][DBLP]
   FCCM, 2004, pp:310-311 [Conf]
   
3. Yousef El-Kurdi, Warren J. Gross, Dennis Giannacopoulos
   Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs. [Citation Graph (0, 0)][DBLP]
   FCCM, 2006, pp:293-294 [Conf]
   
4. Shaoqiang Bi, Warren J. Gross, Wei Wang, Asim J. Al-Khalili, M. N. S. Swamy
   An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction. [Citation Graph (0, 0)][DBLP]
   IWSOC, 2005, pp:396-399 [Conf]
   
5. Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak
   Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes. [Citation Graph (0, 0)][DBLP]
   IEEE Transactions on Communications, 2006, v:54, n:6, pp:1143- [Journal]
   
6. Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak
   Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes. [Citation Graph (0, 0)][DBLP]
   IEEE Transactions on Communications, 2006, v:54, n:7, pp:1224-1234 [Journal]
   
7. Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak
   Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed-Solomon Decoding. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:309-318 [Journal]
   
8. 
   Evaluation of a High-Level-Language Methodology for High-Performance Reconfigurable Computers. [Citation Graph (, )][DBLP]
   
   
9. 
   Configurable Flow Models for FPGA Particle Graphics Engines. [Citation Graph (, )][DBLP]
   
   
10. 
    Accelerating a Medical 3D Brain MRI Analysis Algorithm using a High-Performance Reconfigurable Computer. [Citation Graph (, )][DBLP]
    
    
11. 
    Stochastic Decoding of LDPC Codes over GF(q). [Citation Graph (, )][DBLP]
    
    
12. 
    Survey of Stochastic Computation on Factor Graphs. [Citation Graph (, )][DBLP]
    
    
13. 
    Switching Activity in Stochastic Decoders. [Citation Graph (, )][DBLP]
    
    
14. 
    Design and FPGA implementation of iterative decoders for codes on graphs. [Citation Graph (, )][DBLP]
    
    
15. 
    A Relaxed Half-Stochastic Iterative Decoder for LDPC Codes. [Citation Graph (, )][DBLP]
    
    
16. 
    A stochastic particle-based biological system simulator. [Citation Graph (, )][DBLP]
    
    
17. 
    An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding. [Citation Graph (, )][DBLP]
    
    
18. 
    Bidirectional interleavers for LDPC decoders using transmission gates. [Citation Graph (, )][DBLP]
    
    
19. 
    Tracking Forecast Memories in stochastic decoders. [Citation Graph (, )][DBLP]