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Aitzol Zuloaga: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Unai Bidarte, Armando Astarloa, Aitzol Zuloaga, Jaime Jimenez, Iñigo Martínez de Alegría
    Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:497-506 [Conf]
  2. Armando Astarloa, Jesús Lázaro, Unai Bidarte, José Luis Martín, Aitzol Zuloaga
    A Self-Reconfiguration Framework for Multiprocessor CSoPCs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1124-1126 [Conf]
  3. Aitzol Zuloaga, José Luis Martín, Joseba Ezquerra
    Hardware Architecture for Optical Flow Estimation in Real Time. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 1998, pp:972-976 [Conf]
  4. Jagoba Arias, Jesús Lázaro, Aitzol Zuloaga, Jaime Jimenez
    Doppler Location Algorithm for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    International Conference on Wireless Networks, 2004, pp:509-514 [Conf]
  5. Armando Astarloa, Jesús Lázaro, Jagoba Arias, Unai Bidarte, Aitzol Zuloaga
    Co-simulation Virtual Platform for Reconfigurable Multiprocessor Hybrid Cores Development. [Citation Graph (0, 0)][DBLP]
    MSV/AMCS, 2004, pp:17-22 [Conf]
  6. José Luis Martín, Aitzol Zuloaga, Josu Cruzado
    Software Workbench for Movement Estimation based on Optical Flow Computation. [Citation Graph (0, 0)][DBLP]
    VIIP, 2001, pp:517-522 [Conf]
  7. Jagoba Arias, Eduardo Santos, Itziar Marin, Jaime Jimenez, Jesús Lázaro, Aitzol Zuloaga
    Node Synchronization in Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ICWMC, 2006, pp:50- [Conf]
  8. José L. Martín-Sánchez, Aitzol Zuloaga, Carlos Cuadrado, Jesús Lázaro, Unai Bidarte
    Hardware implementation of optical flow constraint equation using FPGAs. [Citation Graph (0, 0)][DBLP]
    Computer Vision and Image Understanding, 2005, v:98, n:3, pp:462-490 [Journal]
  9. Jesús Lázaro, Jagoba Arias, José Luis Martín, Aitzol Zuloaga, Carlos Cuadrado
    SOM Segmentation of gray scale images for optical recognition. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition Letters, 2006, v:27, n:16, pp:1991-1997 [Journal]
  10. Jaime Jimenez, José Luis Martín, Aitzol Zuloaga, Unai Bidarte, Jagoba Arias
    Comparison of two designs for the multifunction vehicle bus. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:797-805 [Journal]
  11. Armando Astarloa, Unai Bidarte, Jesús Lázaro, Aitzol Zuloaga, Jagoba Arias
    Multiprocessor SoPC-Core for FAT volume computation. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:10, pp:421-434 [Journal]
  12. Jagoba Arias, Aitzol Zuloaga, Jesús Lázaro, Jon Andreu, Armando Astarloa
    Malguki: an RSSI based ad hoc location algorithm. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:8, pp:403-409 [Journal]
  13. Jagoba Arias, Jesús Lázaro, Aitzol Zuloaga, Jaime Jimenez, Armando Astarloa
    GPS-less location algorithm for wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 2007, v:30, n:14-15, pp:2904-2916 [Journal]
  14. Jesús Lázaro, Jagoba Arias, Armando Astarloa, Unai Bidarte, Aitzol Zuloaga
    Hardware architecture for a general regression neural network coprocessor. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 2007, v:71, n:1-3, pp:78-87 [Journal]
  15. Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, José Luis Martín, Jesús Lázaro, Jaime Jimenez
    Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:9, pp:629-643 [Journal]

  16. A Novel Technique for Low Latency Data Gathering in Wireless Sensor Networks. [Citation Graph (, )][DBLP]

  17. DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus. [Citation Graph (, )][DBLP]

  18. AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. [Citation Graph (, )][DBLP]

  19. PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. [Citation Graph (, )][DBLP]

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