Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2006, volume: 25, number: 5

1. Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
   Using simulation and satisfiability to compute flexibilities in Boolean networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:743-755 [Journal]
   
2. Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, Seth Copen Goldstein
   Hardware compilation of application-specific memory-access interconnect. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:756-771 [Journal]
   
3. Philip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh
   Optimal register sharing for high-level synthesis of SSA form programs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:772-779 [Journal]
   
4. Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain
   On partitioning and symbolic model checking. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:780-788 [Journal]
   
5. T. Sasao
   Analysis and synthesis of weighted-sum functions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:789-796 [Journal]
   
6. Jaime Jimenez, José Luis Martín, Aitzol Zuloaga, Unai Bidarte, Jagoba Arias
   Comparison of two designs for the multifunction vehicle bus. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:797-805 [Journal]
   
7. Ying Yi, R. Woods
   Hierarchical synthesis of complex DSP functions using IRIS. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:806-820 [Journal]
   
8. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De
   Formal derivation of optimal active shielding for low-power on-chip buses. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:821-836 [Journal]
   
9. Srinivas Bodapati, Farid N. Najm
   High-level current macro model for logic blocks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:837-855 [Journal]
   
10. Yan Feng, Dinesh P. Mehta
    Module relocation to obtain feasible constrained floorplans. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:856-866 [Journal]
    
11. Premachandran R. Menon, Weifeng Xu, Russell Tessier
    Design-specific path delay testing in lookup-table-based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:867-877 [Journal]
    
12. Haralampos-G. D. Stratigopoulos, Yiorgos Makris
    Concurrent detection of erroneous responses in linear analog circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:878-891 [Journal]
    
13. Kanak Agarwal, Dennis Sylvester, David Blaauw
    Modeling and analysis of crosstalk noise in coupled RLC interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:892-901 [Journal]
    
14. Rüdiger Ebendt, Rolf Drechsler
    Effect of improved lower bounds in dynamic BDD reordering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:902-909 [Journal]
    
15. Kooho Jung, William R. Eisenstadt, Robert M. Fox
    SPICE-based mixed-mode S-parameter calculations for four-port and three-port circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:909-913 [Journal]
    
16. Hong-Sik Kim, Sungho Kang
    Increasing encoding efficiency of LFSR reseeding-based test compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:913-917 [Journal]
    
17. Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
    Practical repeater insertion for low power: what repeater library do we need? [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:917-924 [Journal]
    
18. E. S. J. Martens, Georges G. E. Gielen
    Analyzing continuous-time /spl Delta//spl Sigma/ Modulators with generic behavioral models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:924-932 [Journal]
    
19. Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
    An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:932-938 [Journal]