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Leomar S. da Rosa Jr.:
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- Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
DAG based library-free technology mapping. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2007, pp:293-298 [Conf]
- Leomar S. da Rosa Jr., Flávio Rech Wagner, Luigi Carro, Alexandre Carissimi, André Inácio Reis
Scheduling Policy Costs on a JAVA Microcontroller. [Citation Graph (0, 0)][DBLP] OTM Workshops, 2003, pp:520-533 [Conf]
- Leomar S. da Rosa Jr., Felipe S. Marques, Tiago M. G. Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
Fast disjoint transistor networks from BDDs. [Citation Graph (0, 0)][DBLP] SBCCI, 2006, pp:137-142 [Conf]
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. [Citation Graph (, )][DBLP]
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. [Citation Graph (, )][DBLP]
Switch level optimization of digital CMOS gate networks. [Citation Graph (, )][DBLP]
A comparative study of CMOS gates with minimum transistor stacks. [Citation Graph (, )][DBLP]
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