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Title:
Author:
Luigi Carro: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Júlio C. B. de Mattos, Stephan Wong, Luigi Carro
    The Molen FemtoJava Engine. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:19-22 [Conf]
  2. Lisane B. de Brisolara, Leandro Buss Becker, Luigi Carro, Flávio Rech Wagner, Carlos Eduardo Pereira, Ricardo Reis
    Comparing high-level modeling approaches for embedded system design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:986-989 [Conf]
  3. César A. M. Marcon, André Borin Suarez, Altamiro Amadeu Susin, Luigi Carro, Flávio Rech Wagner
    Time and energy efficient mapping of embedded applications onto NoCs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:33-38 [Conf]
  4. Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell
    TI-BIST: a temperature independent analog BIST for switched-capacitor filters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:78-83 [Conf]
  5. Fernanda Lima Kastensmidt, Gustavo Neuberger, Luigi Carro, Ricardo Reis
    Designing and testing fault-tolerant techniques for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:419-432 [Conf]
  6. Antonio Carlos Schneider Beck, Luigi Carro
    Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:732-737 [Conf]
  7. Luigi Carro, Marcelo Negreiros
    Efficient Analog Test Methodology Based on Adaptive Algorithms. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:32-37 [Conf]
  8. Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz Reis
    Designing fault tolerant systems into SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:650-655 [Conf]
  9. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Ultimate low cost analog BIST. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:570-573 [Conf]
  10. Luigi Carro, Márcio Eduardo Kreutz, Flávio Rech Wagner, Márcio Oyamada
    System Synthesis for Multiprocessor Embedded Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:697-702 [Conf]
  11. Luigi Carro, Adão Antônio de Souza Jr., Marcelo Negreiros, Gabriel Parmegiani Jahn, Denis Teixeira Franco
    Non-Linear Components for Mixed Circuits Analog Front-End. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:544-0 [Conf]
  12. Érika F. Cota, Luigi Carro, Marcelo Lubaszewski
    A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:184-188 [Conf]
  13. Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu
    Test Planning and Design Space Exploration in a Core-Based Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:478-485 [Conf]
  14. Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski
    Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:226-0 [Conf]
  15. Sérgio Akira Ito, Luigi Carro, Ricardo Pezzuol Jacobi
    System Design Based on Single Language and Single-Chip Java ASIP Microcontroller. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:703-0 [Conf]
  16. Adão Antônio de Souza Jr., Luigi Carro
    Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:10-15 [Conf]
  17. Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda
    On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1290-1295 [Conf]
  18. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Low Cost Analog Testing of RF Signal Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:292-297 [Conf]
  19. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Noise Figure Evaluation Using Low Cost BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:158-163 [Conf]
  20. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    An improved RF loopback for test time reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:646-651 [Conf]
  21. Carlos Arthur Lang Lisbôa, Luigi Carro
    Arithmetic Operators Robust to Multiple Simultaneous Upsets. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:289-297 [Conf]
  22. Erik Schüler, Luigi Carro
    Reliable Digital Circuits Design using Sigma-Delta Modulated Signals. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:314-324 [Conf]
  23. Adão Antônio de Souza Jr., Luigi Carro
    Robust Low-Cost Analog Signal Acquisition with Self-Test Capabilities. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:239-247 [Conf]
  24. Á. Michels, L. Petroli, Carlos Arthur Lang Lisbôa, Fernanda Gusmão de Lima Kastensmidt, Luigi Carro
    SET Fault Tolerant Combinational Circuits Based on Majority Logic. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:345-352 [Conf]
  25. Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante
    Online hardening of programs against SEUs and SETs. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:280-290 [Conf]
  26. Luigi Carro, G. A. Pereira, C. Alba, Altamiro Amadeu Susin
    System Design using ASIPs. [Citation Graph (0, 0)][DBLP]
    ECBS, 1996, pp:80-85 [Conf]
  27. Luigi Carro, Altamiro Amadeu Susin
    A Risc Architecture to Explore HW/SW Parallelism in HW/SW Co-Design. [Citation Graph (0, 0)][DBLP]
    ECBS, 1996, pp:382-388 [Conf]
  28. Luigi Carro, Denis Teixeira Franco
    FPGA Based Systems with Linear and Non-Linear Signal Processing Capabilities. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1260-0 [Conf]
  29. Luigi Carro
    Architecture Considerations for Mixed Signals FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:245- [Conf]
  30. Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz Reis
    Reducing pin and area overhead in fault-tolerant FPGA-based designs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:108-117 [Conf]
  31. Eric E. Fabris, Luigi Carro, Sergio Bampi
    Analog Signal Processing Reconfiguration for Systems-on-Chip Using a Fixed Analog Cell Approach. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1136-1138 [Conf]
  32. Erik Schüler, Luigi Carro
    A Low Power FPAA for Wide Band Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:970-974 [Conf]
  33. C. Alba, Luigi Carro, A. Lima, Altamiro Amadeu Susin
    Embedded Systems Design with Frontend Compilers. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:200-0 [Conf]
  34. Lisane B. de Brisolara, Leandro Buss Becker, Luigi Carro, Flávio Rech Wagner, Carlos Eduardo Pereira
    Evaluating High-Level Models for Real-Time Embedded Systems Design. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:277-286 [Conf]
  35. Luigi Carro, Flávio Rech Wagner, Márcio Eduardo Kreutz, Márcio Oyamada
    A Design Methodology for Embedded Systems based on Multiple Processors. [Citation Graph (0, 0)][DBLP]
    DIPES, 2000, pp:33-42 [Conf]
  36. Edgard de Faria Corrêa, Eduardo W. Basso, Gustavo R. Wilke, Flávio Rech Wagner, Luigi Carro
    The Implications of Real-Time Behavior in Networks-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:307-316 [Conf]
  37. Júlio C. B. de Mattos, Lisane B. de Brisolara, Renato Fernandes Hentschke, Luigi Carro, Flávio Rech Wagner
    Design Space Exploration with Automatic Generation of IP-Based Embedded Software. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:237-246 [Conf]
  38. Fernanda Lima, Marcelo O. Johann, José Luís Almada Güntzel, Eduardo D'Avila, Luigi Carro, Ricardo Augusto da Luz Reis
    Designing a Mask Programmable Matrix for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:439-446 [Conf]
  39. Luigi Carro, André C. Nácul, Daniel Janner, Marcelo Lubaszewski
    Built-in Test of Analog Non-Linear Circuits in a SOC Environment. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:437-448 [Conf]
  40. Flávio Rech Wagner, Márcio Oyamada, Luigi Carro, Márcio Eduardo Kreutz
    Object-Oriented Modeling and Co-Simulation of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:497-508 [Conf]
  41. D. Franco, Luigi Carro
    FPGA Architecture Comparison for Non-Conventional Signal Processing. [Citation Graph (0, 0)][DBLP]
    IJCNN (2), 2000, pp:55-58 [Conf]
  42. Fernanda Gusmão de Lima, Luigi Carro, Raoul Velazco, Ricardo Augusto da Luz Reis
    Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:194- [Conf]
  43. Carlos Arthur Lang Lisbôa, Luigi Carro
    An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:180- [Conf]
  44. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    A Statistical Sampler for a New On-line Analog Test Method. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:79-0 [Conf]
  45. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Low Cost On-Line Testing of RF Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:73-78 [Conf]
  46. Erik Schüler, Luigi Carro
    Increasing Fault Tolerance to Multiple Upsets Using Digital Sigma-Delta Modulators. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:255-259 [Conf]
  47. Arthur Pereira Frantz, Luigi Carro, Érika F. Cota, Fernanda Lima Kastensmidt
    Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:191-192 [Conf]
  48. Antonio Carlos Schneider Beck, Luigi Carro
    Application of Binary Translation to Java Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  49. João Cláudio Soares Otero, Flávio Rech Wagner, Luigi Carro
    Reconfiguration of embedded Java applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  50. A. B. Soares, Luigi Carro, Altamiro Amadeu Susin
    Reconfigurable communications for image processing applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  51. Rodrigo Ferrugem Cardoso, Márcio Eduardo Kreutz, Luigi Carro, Altamiro Amadeu Susin
    Design space exploration on heterogeneous network-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:428-431 [Conf]
  52. Luigi Carro, Edgard de Faria Corrêa, R. Cardozo, Fernando Moraes, Sergio Bampi
    Exploiting reconfigurability for low-power control of embedded processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:421-424 [Conf]
  53. Eric E. Fabris, Luigi Carro, Sergio Bampi
    An analog signal interface with constant performance for SoCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:773-776 [Conf]
  54. Rafael Krapf, Luigi Carro
    Efficient signal processing in embedded Java systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:61-64 [Conf]
  55. Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Altamiro Amadeu Susin, Ney Laert Vilar Calazans
    Energy and latency evaluation of NoC topologies. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5866-5869 [Conf]
  56. Josias O. Mainardi, Adão Antônio de Souza Jr., Luigi Carro, Altamiro Amadeu Susin
    A comparison of totally digital ADCs for SOCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:641-644 [Conf]
  57. Adão Antônio de Souza Jr., Luigi Carro, Jawad Tousaad
    Adaptive processing applied to the design of highly digital analog interfaces. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5597-5600 [Conf]
  58. O. Betat, L. Carro
    Comparison of digital linearization methods for embedded sensor interfaces. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:429-432 [Conf]
  59. J. C. B. Mattos, L. Carro
    Efficient architecture for FPGA-based microcontrollers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:805-808 [Conf]
  60. Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro
    Transparent Dataflow Execution for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:47-54 [Conf]
  61. Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski
    Power-aware NoC Reuse on the Testing of Core-based Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:612-621 [Conf]
  62. Leomar S. da Rosa Jr., Flávio Rech Wagner, Luigi Carro, Alexandre Carissimi, André Inácio Reis
    Scheduling Policy Costs on a JAVA Microcontroller. [Citation Graph (0, 0)][DBLP]
    OTM Workshops, 2003, pp:520-533 [Conf]
  63. Marcio F. da S. Oliveira, Lisane B. de Brisolara, Luigi Carro, Flávio Rech Wagner
    Early Embedded Software Design Space Exploration Using UML-Based Estimation. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2006, pp:24-32 [Conf]
  64. Antonio Carlos Schneider Beck, Mateus B. Rutzig, Luigi Carro
    Advantages of Java Processors in Cache Performance and Power for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:321-330 [Conf]
  65. Júlio C. B. de Mattos, Antonio Carlos Schneider Beck, Luigi Carro, Flávio Rech Wagner
    Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:303-312 [Conf]
  66. Júlio C. B. de Mattos, Emilena Specht, Bruno Neves, Luigi Carro
    Making object oriented efficient for embedded system applications. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:104-109 [Conf]
  67. Antonio Carlos Schneider Beck, Mateus B. Rutzig, Luigi Carro
    Cache performance impacts for stack machines in embedded systems. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:155-160 [Conf]
  68. Carlos Arthur Lang Lisbôa, Erik Schüler, Luigi Carro
    Going beyond TMR for protection against multiple faults. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:80-85 [Conf]
  69. Arthur Pereira Frantz, Fernanda Lima Kastensmidt, Luigi Carro, Érika F. Cota
    Evaluation of SEU and crosstalk effects in network-on-chip switches. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:202-207 [Conf]
  70. Eric E. Fabris, Luigi Carro, Sergio Bampi
    Modeling and designing high performance analog reconfigurable circuits. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:49-54 [Conf]
  71. Antonio Carlos Schneider Beck, Luigi Carro
    A VLIW low power Java processor for embedded applications. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:157-162 [Conf]
  72. Ricardo C. G. da Silva, Henri Boudinov, Luigi Carro
    A cell library for low power high performance CMOS voltage-mode quaternary logic. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:167-172 [Conf]
  73. Marcelo Moraes, Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski
    A constraint-based solution for on-line testing of processors embedded in real-time applications. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:68-73 [Conf]
  74. Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Flávio Rech Wagner, Altamiro Amadeu Susin
    Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:190-195 [Conf]
  75. Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro
    Exploiting Java through binary translation for low power embedded reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:92-97 [Conf]
  76. Marcelo Negreiros, Erik Schüler, Luigi Carro, Altamiro Amadeu Susin
    Testing RF Signal Paths Using Spectral Analysis and Subsampling. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:329-0 [Conf]
  77. Eric E. Fabris, Luigi Carro, Sergio Bampi
    A Universal High-Performance Analog Interface for Signal Processing SOCs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:137-0 [Conf]
  78. Antonio C. S. Beck Filho, Júlio C. B. de Mattos, Flávio Rech Wagner, Luigi Carro
    CACO-PS: A General Purpose Cycle-Accurate Configurable Power Simulator. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:349-354 [Conf]
  79. Antonio Carlos Schneider Beck, Luigi Carro
    Low Power Java Processor for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:239-0 [Conf]
  80. Adão Antônio de Souza Jr., Luigi Carro
    An All-Digital ADC for Instrumentation within SOCs. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:398-403 [Conf]
  81. Érika F. Cota, Márcio Eduardo Kreutz, Cesar Albenes Zeferino, Luigi Carro, Marcelo Lubaszewski, Altamiro Amadeu Susin
    The Impact of NoC Reuse on the Testing of Core-based Systems. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:128-133 [Conf]
  82. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Ultra Low Cost Analog BIST Using Spectral Analysis. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:77-82 [Conf]
  83. Marcelo Negreiros, Adão Antônio de Souza Jr., Luigi Carro, Altamiro Amadeu Susin
    RF Digital Signal Generation Beyond Nyquist. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:15-22 [Conf]
  84. Luigi Carro
    Adding value to design and test through education: What are the challenges? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:388- [Journal]
  85. Luigi Carro, Marcelo Negreiros, Gabriel Parmegiani Jahn, Adão Antônio de Souza Jr., Denis Teixeira Franco
    Circuit-Level Considerations for Mixed-Signal Programmable Components. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:76-84 [Journal]
  86. Sérgio Akira Ito, Luigi Carro, Ricardo Pezzuol Jacobi
    Making Java Work for Microcontroller Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:5, pp:100-110 [Journal]
  87. Fernanda Lima Kastensmidt, Gustavo Neuberger, Renato Fernandes Hentschke, Luigi Carro, Ricardo Reis
    Designing Fault-Tolerant Techniques for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:552-562 [Journal]
  88. Flávio Rech Wagner, Wander O. Cesário, Luigi Carro, Ahmed Amine Jerraya
    Strategies for the integration of hardware and software IP components in embedded systems-on-chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:37, n:4, pp:223-252 [Journal]
  89. Márcio Eduardo Kreutz, Cesar Albenes Zeferino, Luigi Carro, Altamiro Amadeu Susin
    Análise e Seleção de Redes de Interconexão para Síntese de Sistemas no Ambiente S3E2S. [Citation Graph (0, 0)][DBLP]
    RITA, 2001, v:8, n:1, pp:83-101 [Journal]
  90. Fernanda Lima Kastensmidt, Gustavo Neuberger, Luigi Carro, Ricardo Reis
    Desenvolvimento de Técnicas de Tolerância à Falhas para Componentes Programáveis por SRAM. [Citation Graph (0, 0)][DBLP]
    RITA, 2005, v:12, n:1, pp:47-60 [Journal]
  91. Érika F. Cota, Luigi Carro, Marcelo Lubaszewski
    Reusing an on-chip network for the test of core-based systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:4, pp:471-499 [Journal]
  92. Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Luigi Carro, Ricardo Augusto da Luz Reis
    A multiple bit upset tolerant SRAM memory. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:577-590 [Journal]
  93. Kai Huang, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya
    Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:39-42 [Conf]
  94. E. L. Rhod, C. A. Lisboa, Luigi Carro
    A low-SER efficient core processor architecture for future technologies. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1448-1453 [Conf]
  95. Eric E. Fabris, Luigi Carro, Sergio Bampi
    Reconfigurable analog interface for mixed signal SOC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  96. Júlio C. B. de Mattos, Antonio Carlos Schneider Beck, Luigi Carro
    Object-Oriented Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:69-74 [Conf]
  97. Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro
    Automatic Dataflow Execution with Reconfiguration and Dynamic Instruction Merging. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:30-35 [Conf]
  98. R. C. Goncalves da Silva, H. I. Boudinov, L. Carro
    A low power high performance CMOS voltage-mode quaternary full adder. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:187-191 [Conf]
  99. Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro
    Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:449-454 [Conf]
  100. C. A. Lisboa, Marcelo Ienczczak Erigson, Luigi Carro
    System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:165-172 [Conf]
  101. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Digital Generation of Signals for Low Cost RF BIST. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:49-54 [Conf]
  102. Erik Schüler, Marcelo Negreiros, Pascal Nouet, Luigi Carro
    A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:21-28 [Conf]
  103. Erik Schüler, Daniel Scain Farenzena, Luigi Carro
    Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:137-144 [Conf]
  104. Flávio Rech Wagner, Luigi Carro
    Embedded SW Design Space Exploration and Automation using UML-Based Tools. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:437-440 [Conf]
  105. Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda
    On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  106. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Noise Figure Evaluation Using Low Cost BIST [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  107. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Testing analog circuits using spectral analysis. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:10, pp:937-944 [Journal]
  108. Victor F. Gomes, Antonio Carlos Schneider Beck, Luigi Carro
    Trading Time and Space on Low Power Embedded Architectures with Dynamic Instruction Merging. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:3, pp:249-258 [Journal]
  109. Maria Da Gloria Flores, Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin, Felipe R. Clayton, Cristiano Benevento
    Low Cost BIST for Static and Dynamic Testing of ADCs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:283-290 [Journal]
  110. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Low Cost On-Line Testing Strategy for RF Circuits. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:4, pp:417-427 [Journal]
  111. Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro
    Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:1, pp:47-54 [Journal]
  112. Erik Schüler, Marcelo Ienczczak Erigson, Luigi Carro
    Functionally Fault-tolerant DSP Microprocessor using Sigma-delta Modulated Signals. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:4, pp:275-292 [Journal]

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  119. Adaptive Processing Architectures for the Ultimate Scaling of the CMOS World. [Citation Graph (, )][DBLP]


  120. Reducing interconnection cost in coarse-grained dynamic computing through multistage network. [Citation Graph (, )][DBLP]


  121. On the Use of Software Quality Metrics to Improve Physical Properties of Embedded Systems. [Citation Graph (, )][DBLP]


  122. A fast error correction technique for matrix multiplication algorithms. [Citation Graph (, )][DBLP]


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  127. Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design. [Citation Graph (, )][DBLP]


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  129. Introduction to the Future of Reconfigurable Computing and Processor Architectures. [Citation Graph (, )][DBLP]


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  137. Resource-and-time-aware test strategy for configurable quaternary logic blocks. [Citation Graph (, )][DBLP]


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  139. Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC. [Citation Graph (, )][DBLP]


  140. Transparent acceleration of data dependent instructions for general purpose processors. [Citation Graph (, )][DBLP]


  141. Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms. [Citation Graph (, )][DBLP]


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  145. The Case for Interpreted Languages in Sensor Networks. [Citation Graph (, )][DBLP]


  146. New Challenges for Designers of Fault Tolerant Embedded Systems Based on Future Technologies. [Citation Graph (, )][DBLP]


  147. Software Quality Metrics and their Impact on Embedded Software. [Citation Graph (, )][DBLP]


  148. Crosstalk- and SEU-Aware Networks on Chips. [Citation Graph (, )][DBLP]


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