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André Inácio Reis: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Felipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
    A new approach to the use of satisfiability in false path detection. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:308-311 [Conf]
  2. João Daniel Togni, Renato P. Ribas, Maria Lucia Blamck Lisboa, André Inácio Reis
    Tool integration using the web-services approach. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:337-340 [Conf]
  3. Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
    DAG based library-free technology mapping. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:293-298 [Conf]
  4. Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
    Modeling and estimating leakage current in series-parallel CMOS networks. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:269-274 [Conf]
  5. Felipe R. Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
    Exact lower bound for the number of switches in series to implement a combinational logic cell. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:357-362 [Conf]
  6. Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
    Modeling Subthreshold Leakage Current in General Transistor Networks. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:512-513 [Conf]
  7. Felipe R. Schneider, Vinícius P. Correia, Renato P. Ribas, André Inácio Reis
    Comparing Transistor-Level Implementations of 4-Input Logic Functions. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:361-365 [Conf]
  8. Vinícius P. Correia, Marcelo Lubaszewski, André Inácio Reis
    SIFU! - A Didactic Stuck-at Fault Simulator. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:93-94 [Conf]
  9. Vinícius P. Correia, André Inácio Reis
    A Tutorial Tool for Switch Logic. [Citation Graph (0, 0)][DBLP]
    MSE, 2001, pp:28-29 [Conf]
  10. Leomar S. da Rosa Jr., Flávio Rech Wagner, Luigi Carro, Alexandre Carissimi, André Inácio Reis
    Scheduling Policy Costs on a JAVA Microcontroller. [Citation Graph (0, 0)][DBLP]
    OTM Workshops, 2003, pp:520-533 [Conf]
  11. R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, André Inácio Reis
    Asynchronous circuit design on reconfigurable devices. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:20-25 [Conf]
  12. Leomar S. da Rosa Jr., Felipe S. Marques, Tiago M. G. Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
    Fast disjoint transistor networks from BDDs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:137-142 [Conf]
  13. Vinícius Correia, André Reis
    Advanced technology mapping for standard-cell generators. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:254-259 [Conf]
  14. Mário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas
    Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:181-185 [Conf]
  15. Renato E. B. Poli, Felipe R. Schneider, Renato P. Ribas, André Inácio Reis
    Unified Theory to Build Cell-Level Transistor Networks from BDDs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:199-204 [Conf]
  16. Renato P. Ribas, André Inácio Reis, Marcelo Lubaszewski
    Concepção de Circuitos e Sistemas Integrados. [Citation Graph (0, 0)][DBLP]
    RITA, 2001, v:8, n:1, pp:7-21 [Journal]
  17. Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
    Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:474-484 [Conf]

  18. KL-Cuts: A new approach for logic synthesis targeting multiple output blocks. [Citation Graph (, )][DBLP]


  19. Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. [Citation Graph (, )][DBLP]


  20. Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. [Citation Graph (, )][DBLP]


  21. Switch level optimization of digital CMOS gate networks. [Citation Graph (, )][DBLP]


  22. Routing Resistance Influence in Loading Effect on Leakage Analysis. [Citation Graph (, )][DBLP]


  23. A comparative study of CMOS gates with minimum transistor stacks. [Citation Graph (, )][DBLP]


  24. What about the IP of your IP?: an introduction to intellectual property law for engineers and scientists. [Citation Graph (, )][DBLP]


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