Henry Cox Synthesizing Circuits with Implicit Testability Constraints. [Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 1995, v:12, n:2, pp:16-23 [Journal]
Henry Cox, Janusz Rajski A method of fault analysis for test generation and fault diagnosis. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:7, pp:813-833 [Journal]
Henry Cox, Janusz Rajski On necessary and nonconflicting assignments in algorithmic test pattern generation. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:515-530 [Journal]
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