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Vinod K. Agarwal :
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Arun K. Somani , Vinod K. Agarwal An Efficient VLSI Dictionary Machine. [Citation Graph (1, 0)][DBLP ] ISCA, 1984, pp:142-150 [Conf ] Arun K. Somani , Vinod K. Agarwal An Efficient Unsorted VLSI Dictionary Machine. [Citation Graph (1, 0)][DBLP ] IEEE Trans. Computers, 1985, v:34, n:9, pp:841-852 [Journal ] Vinod K. Agarwal Embedded Test and Measurement Critical for Deep Submicron Technology. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1997, pp:2-0 [Conf ] Michel Dagenais , Vinod K. Agarwal , Nicholas C. Rumin The McBOOLE logic minimizer. [Citation Graph (0, 0)][DBLP ] DAC, 1985, pp:667-673 [Conf ] Oryal Tanir , Vinod K. Agarwal , P. C. P. Bhatt DASE: An Environment for System Level Telecommunication Design Exploration and Modelling. [Citation Graph (0, 0)][DBLP ] CAST, 1994, pp:302-318 [Conf ] Kaiyuan Huang , Vinod K. Agarwal , Laurence E. LaForge Wafer Testing with Pairwise Comparisons. [Citation Graph (0, 0)][DBLP ] FTCS, 1992, pp:374-383 [Conf ] Guoning Liao , Erik R. Altman , Vinod K. Agarwal , Guang R. Gao A Comparative Study of Multiprocessor List Scheduling Heuristics. [Citation Graph (0, 0)][DBLP ] HICSS (1), 1994, pp:68-77 [Conf ] Shashank S. Nemawarkar , Ramaswamy Govindarajan , Guang R. Gao , Vinod K. Agarwal Performance Evaluation of Latency Tolerant Architectures. [Citation Graph (0, 0)][DBLP ] ICCI, 1992, pp:183-186 [Conf ] Erik R. Altman , Vinod K. Agarwal , Guang R. Gao A Novel Methodology Using Genetic Algorithms for the Design of Caches and Cache Replacement Policy. [Citation Graph (0, 0)][DBLP ] ICGA, 1993, pp:392-399 [Conf ] Morie E. Malowany , Gordon W. Roberts , Vinod K. Agarwal VAMP: A Hierarchical Framework for Design for Manufacturability. [Citation Graph (0, 0)][DBLP ] ISCAS, 1994, pp:141-144 [Conf ] Krishnaiyan Thulasiraman , Anindya Das , Kaiyuan Huang , Vinod K. Agarwal Correct diagnosis of almost all faulty units in a multiprocessor system. [Citation Graph (0, 0)][DBLP ] ISCAS (6), 1999, pp:161-164 [Conf ] Vinod K. Agarwal , Janusz Rajski Testing Properties and Applications of Inverter-Free PLA's. [Citation Graph (0, 0)][DBLP ] ITC, 1985, pp:500-507 [Conf ] Henry Cox , André Ivanov , Vinod K. Agarwal , Janusz Rajski On Multiple Fault Coverage and Aliasing Probability Measures. [Citation Graph (0, 0)][DBLP ] ITC, 1988, pp:314-321 [Conf ] Abu S. M. Hassan , Vinod K. Agarwal , Janusz Rajski Testing and Diagnosis of Interconnects Using Boundary Scan Architecture. [Citation Graph (0, 0)][DBLP ] ITC, 1988, pp:126-137 [Conf ] Abu S. M. Hassan , Vinod K. Agarwal , Janusz Rajski , Benoit Nadeau-Dostie Testing of Glue Logic Interconnects Using Boundary Scan Architecture. [Citation Graph (0, 0)][DBLP ] ITC, 1989, pp:700-711 [Conf ] André Ivanov , Vinod K. Agarwal Testability Measures : What Do They Do for ATPG ? [Citation Graph (0, 0)][DBLP ] ITC, 1986, pp:129-139 [Conf ] D. Lambidonis , André Ivanov , Vinod K. Agarwal Fast Signature Computation for Linear Compactors. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:808-817 [Conf ] Michael G. Lamoureux , Vinod K. Agarwal Non-Stuck-At Fault Detection in nMOS Circuits by Region Analysis. [Citation Graph (0, 0)][DBLP ] ITC, 1983, pp:129-137 [Conf ] Koppolu Sasidhar , Abhijit Chatterjee , Vinod K. Agarwal , Joseph L. A. Hughes Distributed Probabilistic Diagnosis of MCMs on Large Area. [Citation Graph (0, 0)][DBLP ] ITC, 1995, pp:208-216 [Conf ] Yvon Savaria , Vinod K. Agarwal , Nicholas C. Rumin , Jeremiah F. Hayes A Design for Machines with Built-In Tolerance to Soft Errors. [Citation Graph (0, 0)][DBLP ] ITC, 1984, pp:649-659 [Conf ] Robert P. Treuer , Vinod K. Agarwal Fault Location Algorithms for Repairable Embedded. [Citation Graph (0, 0)][DBLP ] ITC, 1993, pp:825-834 [Conf ] Dhiren Xavier , Robert C. Aitken , André Ivanov , Vinod K. Agarwal : Experiments on Aliasing in Signature Analysis Registers. [Citation Graph (0, 0)][DBLP ] ITC, 1989, pp:344-354 [Conf ] Yervant Zorian , Vinod K. Agarwal Higher Certainty of Error Coverage by Output Data Modification. [Citation Graph (0, 0)][DBLP ] ITC, 1984, pp:140-147 [Conf ] Shashank S. Nemawarkar , Ramaswamy Govindarajan , Guang R. Gao , Vinod K. Agarwal Performance of Interconnection Network in Multithreaded Architectures. [Citation Graph (0, 0)][DBLP ] PARLE, 1994, pp:823-826 [Conf ] Shashank S. Nemawarkar , Ramaswamy Govindarajan , Guang R. Gao , Vinod K. Agarwal Analysis of Multithreaded Multiprocessors with Distributed Shared Memory. [Citation Graph (0, 0)][DBLP ] SPDP, 1993, pp:114-121 [Conf ] Vinod K. Agarwal Invited Talk: Embedded Test for Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1999, pp:- [Conf ] Vinod K. Agarwal VTS 1999 Keynote Address Embedded Test OR External Test. [Citation Graph (0, 0)][DBLP ] VTS, 1999, pp:2-7 [Conf ] Anindya Das , Krishnaiyan Thulasiraman , Vinod K. Agarwal , K. B. Lakshmanan t/s-Diagnosable Systems: A Characterization and Diagnosis Algorithm. [Citation Graph (0, 0)][DBLP ] WG, 1989, pp:34-45 [Conf ] Oryal Tanir , Vinod K. Agarwal , P. C. P. Bhatt A Specification-Driven Architectural Design Environment. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 1995, v:28, n:6, pp:26-35 [Journal ] Vinod K. Agarwal VTS 1994 Panel Report on BIST for Consumer Products. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 1995, v:12, n:1, pp:12-0 [Journal ] Benoit Nadeau-Dostie , Allan Silburt , Vinod K. Agarwal Serial Interfacing for Embedded-Memory Testing. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 1990, v:7, n:2, pp:52-63 [Journal ] Robert P. Treuer , Vinod K. Agarwal Built-In Self-Diagnosis for Repairable Embedded RAMs. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 1993, v:10, n:2, pp:24-33 [Journal ] Krishnaiyan Thulasiraman , Anindya Das , Kaiyuan Huang , Vinod K. Agarwal Correct Diagnosis of Almost All Faulty Units in a Multiprocessor System. [Citation Graph (0, 0)][DBLP ] Journal of Circuits, Systems, and Computers, 1998, v:8, n:4, pp:473-481 [Journal ] Anindya Das , Krishnaiyan Thulasiraman , K. B. Lakshmanan , Vinod K. Agarwal Distributed Fault diagnosis of a Ring of Processors. [Citation Graph (0, 0)][DBLP ] Parallel Processing Letters, 1993, v:3, n:, pp:195-204 [Journal ] Anindya Das , Krishnaiyan Thulasiraman , Vinod K. Agarwal Diagnosis of t/(t+1)-Diagnosable Systems. [Citation Graph (0, 0)][DBLP ] SIAM J. Comput., 1994, v:23, n:5, pp:895-905 [Journal ] Vinod K. Agarwal Multiple Fault Detection in Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1980, v:29, n:6, pp:518-522 [Journal ] Vinod K. Agarwal , Andy S. F. Fung Multiple Fault Testing of Large Circuits by Single Fault Test Sets. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1981, v:30, n:11, pp:855-865 [Journal ] Vinod K. Agarwal , Gerald M. Masson Resolution-Oriented Fault Interrelationships in Combinational Logic Networks. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1977, v:26, n:11, pp:1170-1175 [Journal ] Vinod K. Agarwal , Gerald M. Masson Recursive Coverage Projection of Test Sets. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1979, v:28, n:11, pp:865-870 [Journal ] Vinod K. Agarwal , Gerald M. Masson A Functional Form Approach to Test Set Coverage in Tree Networks. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1979, v:28, n:1, pp:50-52 [Journal ] Vinod K. Agarwal , Gerald M. Masson Generic Fault Characterizations for Table Look-Up Coverage Bounding. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1980, v:29, n:4, pp:288-299 [Journal ] Anindya Das , Krishnaiyan Thulasiraman , Vinod K. Agarwal , K. B. Lakshmanan Multiprocessor Fault Diagnosis Under Local Constraints. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1993, v:42, n:8, pp:984-988 [Journal ] A. S. Mahmudul Hassan , Vinod K. Agarwal A Fault-Tolerant Modular Architecture for Binary Trees. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1986, v:35, n:4, pp:356-361 [Journal ] Michael C. Howells , Vinod K. Agarwal A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1988, v:37, n:4, pp:463-468 [Journal ] Laurence E. LaForge , Kaiyuan Huang , Vinod K. Agarwal Almost Sure Diagnosis of Almost Every Good Element. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1994, v:43, n:3, pp:295-305 [Journal ] Arun K. Somani , Vinod K. Agarwal Distributed Diagnosis Algorithms for Regular Interconnected Structures. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1992, v:41, n:7, pp:899-906 [Journal ] Arun K. Somani , Vinod K. Agarwal , David Avis A Generalized Theory for System Level Diagnosis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1987, v:36, n:5, pp:538-546 [Journal ] Arun K. Somani , Vinod K. Agarwal , David Avis On the Complexity of Single Fault Set Diagnosability and Diagnosis Problems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1989, v:38, n:2, pp:195-201 [Journal ] Robert P. Treuer , Vinod K. Agarwal , Hideo Fujiwara A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1987, v:36, n:3, pp:369-373 [Journal ] Michel Dagenais , Vinod K. Agarwal , Nicholas C. Rumin McBOOLE: A New Procedure for Exact Logic Minimization. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:229-238 [Journal ] Abu S. M. Hassan , Vinod K. Agarwal , Benoit Nadeau-Dostie , Janusz Rajski BIST of PCB interconnects using boundary-scan architecture. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1278-1288 [Journal ] Kaiyuan Huang , Vinod K. Agarwal , Krishnaiyan Thulasiraman Diagnosis of clustered faults and wafer testing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:136-148 [Journal ] André Ivanov , Vinod K. Agarwal Dynamic testability measures for ATPG. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:5, pp:598-608 [Journal ] André Ivanov , Vinod K. Agarwal An analysis of the probabilistic behavior of linear feedback signature registers. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:10, pp:1074-1088 [Journal ] André Ivanov , Corot W. Starke , Vinod K. Agarwal , Wilfried Daehn , Matthias Gruetzner , Tom W. Williams Iterative algorithms for computing aliasing probabilities. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:260-265 [Journal ] D. Lambidonis , André Ivanov , Vinod K. Agarwal Fast signature computation for BIST linear compactors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:1037-1044 [Journal ] Dhiren Xavier , Robert C. Aitken , André Ivanov , Vinod K. Agarwal Using an asymmetric error model to study aliasing in signature analysis registers. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:1, pp:16-25 [Journal ] Kaiyuan Huang , Vinod K. Agarwal , Laurence E. LaForge , Krishnaiyan Thulasiraman A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:4, pp:363-372 [Journal ] Jacek Jachner , Vinod K. Agarwal Data Flow Anomaly Detection. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Software Eng., 1984, v:10, n:4, pp:432-437 [Journal ] Search in 0.555secs, Finished in 0.558secs