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Publications of Author

1. Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser
   Estimating Energy Consumption for an MPSoC Architectural Exploration. [Citation Graph (0, 0)][DBLP]
   ARCS, 2006, pp:298-310 [Conf]
   
2. Hassan Sbeyti, Smaïl Niar, Lieven Eeckhout
   Adaptive Prefetching for Multimedia Applications in Embedded Systems. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:1350-1351 [Conf]
   
3. Jamel Tayeb, Smaïl Niar
   Adapting EPIC Architecture's Register Stack for Virtual Stack Machines. [Citation Graph (0, 0)][DBLP]
   DSD, 2006, pp:204-210 [Conf]
   
4. Smaïl Niar, Mahamed Adda
   Performances of a Dynamic Threads Scheduler. [Citation Graph (0, 0)][DBLP]
   Euro-Par, 2001, pp:452-456 [Conf]
   
5. Smaïl Niar, Arnaud Freville
   A Parallel Tabu Search Algorithm For The 0-1 Multidimensional Knapsack Problem. [Citation Graph (0, 0)][DBLP]
   IPPS, 1997, pp:512-516 [Conf]
   
6. Smaïl Niar, Lieven Eeckhout, Koenraad De Bosschere
   Comparing Multiported Cache Schemes. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2003, pp:1179-1185 [Conf]
   
7. J. Khan, Y. Elhillali, S. Niar, A. Rivenq
   A Low Speed Digital Correlator Architecture Optimized For Resource Savings. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2006, pp:207-213 [Conf]
   
8. Smaïl Niar, Nicolas Inglart
   Rapid Performance and Power Consumption Estimation Methods for Embedded System Design. [Citation Graph (0, 0)][DBLP]
   IEEE International Workshop on Rapid System Prototyping, 2006, pp:47-53 [Conf]
   
9. Hassan Sbeyti, Smaïl Niar, Lieven Eeckhout
   Pattern-driven prefetching for multimedia applications on embedded processors. [Citation Graph (0, 0)][DBLP]
   Journal of Systems Architecture, 2006, v:52, n:4, pp:199-212 [Journal]
   
10. Lieven Eeckhout, Smaïl Niar, Koen De Bosschere
    Optimal sample length for efficient cache simulation. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2005, v:51, n:9, pp:513-525 [Journal]
    
11. Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser
    An MPSoC Performance Estimation Framework Using Transaction Level Modeling. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2007, pp:525-533 [Conf]
    
12. 
    An MPSoC architecture for the Multiple Target Tracking application in driver assistant system. [Citation Graph (, )][DBLP]
    
    
13. 
    Multi-granularity sampling for simulating concurrent heterogeneous applications. [Citation Graph (, )][DBLP]
    
    
14. 
    A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC. [Citation Graph (, )][DBLP]
    
    
15. 
    Adaptive Sampling for Efficient MPSoC Architecture Simulation. [Citation Graph (, )][DBLP]
    
    
16. 
    A Real Time Signal Processing for an Anticollision Road Radar System. [Citation Graph (, )][DBLP]
    
    
17. 
    An automatic communication synthesis for high level SOC desing using transaction level modelling (poster). [Citation Graph (, )][DBLP]
    
    
18. 
    Driver assistance system design and its optimization for FPGA based MPSoC. [Citation Graph (, )][DBLP]