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Katarina Paulsson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Michael Hübner, Katarina Paulsson, Marcus Stitz, Jürgen Becker
    Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:39-44 [Conf]
  2. Michael Hübner, Katarina Paulsson, Jürgen Becker
    Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  3. Katarina Paulsson, Michael Hübner, Markus Jung, Jürgen Becker
    Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:159-166 [Conf]
  4. Jürgen Becker, Michael Hübner, Katarina Paulsson, Alexander Thomas
    Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:35-42 [Conf]
  5. Katarina Paulsson, Michael Hübner, Jürgen Becker
    On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:173-178 [Conf]
  6. Katarina Paulsson, Michael Hübner, Jürgen Becker
    Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:288-291 [Conf]
  7. Katarina Paulsson, Michael Hübner, Salih Bayar, Jürgen Becker
    Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:1-6 [Conf]

  8. Physical 2D Morphware and Power Reduction Methods for Everyone. [Citation Graph (, )][DBLP]


  9. Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs. [Citation Graph (, )][DBLP]


  10. On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project. [Citation Graph (, )][DBLP]


  11. Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. [Citation Graph (, )][DBLP]


  12. Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization. [Citation Graph (, )][DBLP]


  13. Data path driven waveform-like reconfiguration. [Citation Graph (, )][DBLP]


  14. Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs. [Citation Graph (, )][DBLP]


  15. Towards Novel Approaches in Design Automation for FPGA Power Optimization. [Citation Graph (, )][DBLP]


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