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Jack S. N. Jean: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Joseph A. Fernando, Jack S. N. Jean
Interfacing FPGA/VLSI Processor Arrays. [Citation Graph (0, 0)][DBLP]
ASAP, 1995, pp:230-237 [Conf] - Jack S. N. Jean, Xinzhong Guo, Fei Wang, Lei Song, Ying Zhang
A Study of Mapping Generalized Sliding Window Operations on Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
Engineering of Reconfigurable Systems and Algorithms, 2003, pp:51-57 [Conf] - Xinzhong Guo, Jack S. N. Jean
Design Enumeration of Mapping 2D FFT onto FPGA Based Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
ERSA, 2004, pp:305-306 [Conf] - Fei Wang, Jack S. N. Jean, Shuxia Sun
Aspect Ratio Effects on Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:71-77 [Conf] - Fei Wang, Jack S. N. Jean
Architectural Support for Runtime 2D Partial Reconfiguration. [Citation Graph (0, 0)][DBLP]
ERSA, 2006, pp:231-236 [Conf] - Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko
Accelerating an IR Automatic Target Recognition Application with FPGAs. [Citation Graph (0, 0)][DBLP]
FCCM, 1999, pp:290-291 [Conf] - Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Robert Cook, Jignesh Shah
Dynamic Reconfiguration to Support Concurrent Applications. [Citation Graph (0, 0)][DBLP]
FCCM, 1998, pp:302-303 [Conf] - Hong K. Kim, Jack S. N. Jean
Parallel Optimistic Logic Simulation with Event Lookahead. [Citation Graph (0, 0)][DBLP]
ICPP, 1998, pp:20-27 [Conf] - Hong K. Kim, Jack S. N. Jean
Concurrency Preserving Rartitioning (CPP) for Parallel Logic Simulation. [Citation Graph (0, 0)][DBLP]
Workshop on Parallel and Distributed Simulation, 1996, pp:98-105 [Conf] - Jack S. N. Jean, Xuejun Liang, Karen A. Tomko
Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
PDPTA, 1999, pp:1111-1117 [Conf] - Xuejun Liang, Jack S. N. Jean
Interface Design for the Mapping of Generalized Template Matching on Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
PDPTA, 2000, pp:- [Conf] - Jin Wang, Jack S. N. Jean
Segmentation of Merged Characters by Neural Networks and Shortest-Path. [Citation Graph (0, 0)][DBLP]
SAC, 1993, pp:762-769 [Conf] - Jin Wang, Jack S. N. Jean
Resolving multifont character confusion with neural networks. [Citation Graph (0, 0)][DBLP]
Pattern Recognition, 1993, v:26, n:1, pp:175-187 [Journal] - Jin Wang, Jack S. N. Jean
Segmentation of merged characters by neural networks and shortest path. [Citation Graph (0, 0)][DBLP]
Pattern Recognition, 1994, v:27, n:5, pp:649-658 [Journal] - Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Jignesh Shah, Robert Cook
Dynamic Reconfiguration to Support Concurrent Applications. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1999, v:48, n:6, pp:591-602 [Journal] - Joseph A. Fernando, Jack S. N. Jean
Processor array design with FPGA area constraint. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:253-264 [Journal] - Xuejun Liang, Jack S. N. Jean, Karen A. Tomko
Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
The Journal of Supercomputing, 2001, v:19, n:1, pp:77-91 [Journal] - Xuejun Liang, Jack S. N. Jean
Mapping of generalized template matching onto reconfigurable computers. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:485-498 [Journal]
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