Journals in DBLP

IEEE Trans. VLSI Syst.
2003, volume: 11, number: 3

1. Yiannos Manoli
   Special section on the 2001 International Conference on Computer Design (ICCD). [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:301-302 [Journal]
   
2. Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger
   Static energy reduction techniques for microprocessor caches. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:303-313 [Journal]
   
3. Lu Peng, Jih-Kwon Peir, Qianrong Ma, Konrad Lai
   Address-free memory access based on program syntax correlation of loads and stores. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:314-324 [Journal]
   
4. John Patrick McGregor, Ruby B. Lee
   Architectural techniques for accelerating subword permutations with repetitions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:325-335 [Journal]
   
5. Yu Zheng, Kenneth L. Shepard
   On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:336-344 [Journal]
   
6. Jin Yang, Carl-Johan H. Seger
   Introduction to generalized symbolic trajectory evaluation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:345-353 [Journal]
   
7. Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska
   PITIA: an FPGA for throughput-intensive applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:354-363 [Journal]
   
8. Chun-Gi Lyuh, Taewhan Kim
   High-level synthesis for low power based on network flow method. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:364-375 [Journal]
   
9. Frederik Vermeulen, Francky Catthoor, Lode Nachtergaele, Diederik Verkest, Hugo De Man
   Power-efficient flexible processor architecture for embedded applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:376-385 [Journal]
   
10. Abderrahim Doumar, Hideo Ito
    Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:386-405 [Journal]
    
11. Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
    Current-mode signaling in deep submicrometer global interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:406-417 [Journal]
    
12. Oscal T.-C. Chen, Sandy Wang, Yi-Wen Wu
    Minimization of switching activities of partial products for designing low-power multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:418-433 [Journal]
    
13. Lei Wang, Naresh R. Shanbhag
    Low-power MIMO signal processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:434-445 [Journal]
    
14. Kostas Masselos, Panagiotis Merakos, S. Theoharis, Thanos Stouraitis, Constantinos E. Goutis
    Power efficient data path synthesis of sum-of-products computations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:446-450 [Journal]
    
15. Yu-Liang Wu, Chak-Chung Cheung, David Ihsin Cheng, Hongbing Fan
    Further improve circuit partitioning using GBAW logic perturbation techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:451-460 [Journal]
    
16. Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer
    Buffer delay change in the presence of power and ground noise. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:461-473 [Journal]
    
17. Jin-Hua Hong, Cheng-Wen Wu
    Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:474-484 [Journal]
    
18. Xuejun Liang, Jack S. N. Jean
    Mapping of generalized template matching onto reconfigurable computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:485-498 [Journal]
    
19. J. L. Nunez, S. Jones
    Gbit/s lossless data compression hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:499-510 [Journal]
    
20. Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Andrew A. Kennings, Alan J. Coppola
    Board-level multiterminal net assignment for the partial cross-bar architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:511-514 [Journal]
    
21. Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman
    Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:514-522 [Journal]