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Conferences in DBLP

Engineering of Reconfigurable Systems and Algorithms (ERSA) (ersa)
2006 (conf/ersa/2006)

  1. Chris Rowen
    The Reinvention of the Microprocessor. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:3-6 [Conf]
  2. Chris Rowen
    Using configurable processors for high-efficiency multiple-processor systems. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:7-10 [Conf]
  3. Maya Gokhale, Christopher Rickett, Justin L. Tripp, Chung Hsu, Ronald Scrofano
    Promises and Pitfalls of Reconfigurable Supercomputing. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:11-20 [Conf]
  4. David L. Andrews, Ron Sass, Erik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp
    The Case for High Level Programming Models for Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:21-32 [Conf]
  5. Brian Holland, James Greco, Ian A. Troxel, Gabe Barfield, Vikas Aggarwal, Alan D. George
    Compile- and Run-Time Services for Distributed Hetergeneous Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:33-41 [Conf]
  6. Dirk Koch, Matthiaas Koerber, Jürgen Teich
    Searching RC5-Keys with Distributed Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:42-48 [Conf]
  7. Vincent Nollet, Prabhat Avasare, Diederik Verkest, Henk Corporaal
    Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:49-55 [Conf]
  8. Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci Memik
    A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:56-62 [Conf]
  9. Carlo Amicucci, Fabrizio Ferrandi, Marco D. Santambrogio, Donatella Sciuto
    SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:63-69 [Conf]
  10. Markus Koester, Heiko Kalte, Mario Porrmann
    Relocation and Defragmentation for Heterogeneous Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:70-76 [Conf]
  11. Sebastian Lange, Martin Middendorf
    Cache Architectures for Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:77-83 [Conf]
  12. Yvan Eustache, Jean-Philippe Diguet, Milad El Khodary
    RTOS-Based Hardware Software Communications and Configuration Management in the Context of a Smart Camera. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:84-92 [Conf]
  13. Craig Ulmer, Adrian Javelo
    Floating-Point Unit Reuse in an FPGA Implementation of a Ray-Triangle Intersection Algorithm. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:93-102 [Conf]
  14. Cao Liang, Jing Ma, Xin-Ming Huang
    An FPGA based Co-Design Architecture for MIMO Lattice Decoders. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:103-109 [Conf]
  15. Gerard K. Rauwerda, Gerard J. M. Smit, Casper R. W. van Benthem, Paul M. Heysters
    Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:110-116 [Conf]
  16. Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit
    A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:117-122 [Conf]
  17. José
    Delgado-Frias, Jonathan Larson, Mitchell Myjak: Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:123-129 [Conf]
  18. Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano
    A Parametric Study of Scalable Interconnects on FPGAs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:130-135 [Conf]
  19. Chuan He, Guan Qin, Mi Lu, Wei Zhao
    Group-Alignment based Accurate Floating-Point Summation on FPGAs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:136-142 [Conf]
  20. Volodymyr V. Kindratenko
    Code Partitioning for Reconfigurable High-Performance Computing: A Case Study. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:143-152 [Conf]
  21. Jeoong Sung Park, Hong-Jip Jung, Viktor K. Prasanna
    Efficient FPGA-based Implementations of the MIMO-OFDM Physical Layer. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:153-163 [Conf]
  22. Herwin Chan, Patrick Schaumont, Ingrid Verbauwhede
    Process Isolation for Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:164-170 [Conf]
  23. Marcel van de Burgwal, Gerard J. M. Smit, Gerard K. Rauwerda, Paul M. Heysters
    Hydra: An Energy-efficient and Reconfigurable Network Interface. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:171-177 [Conf]
  24. Muhammad Akhtar Khan, Abdul Hameed, Ahmet T. Erdogan
    Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC). [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:178-183 [Conf]
  25. Chun Hok Ho, Ka Fai Cedric Yiu, Jiaquan Huo, Sven Nordholm, Wayne Luk
    Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:184-190 [Conf]
  26. Joshua Noseworthy, Miriam Leeser
    Efficient Use of Communications Between an FPGAs Embedded Processor and its Reconfigurable Logic. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:191-197 [Conf]
  27. Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi
    Differential Reconfiguration Architecture suitable for a Holographic Memory. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:198-206 [Conf]
  28. Ryan Glabb, Laurent Imbert, Graham A. Jullien, Arnaud Tisserand, Nicolas Veyrat-Charvillon
    Multi-Mode Operator for SHA-2 Hash Functions. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:207-210 [Conf]
  29. Saumil Merchant, Gregory D. Peterson, Seong Kong
    Intrinsic Embedded Hardware Evolution of Block-based Neural Networks. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:211-214 [Conf]
  30. Yu Bi, Gregory D. Peterson, G. Lee Warren, Robert J. Harrison
    Hardware Acceleration of Parallel Lagged-Fibonacci Pseudo Random Number Generation. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:215-218 [Conf]
  31. Mohammad Samie, Gabriel Dragffy, Ebrahim Farjah
    Metamorphic Memory Based Bio-Inspired Reconfigurable Celluar Systems. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:219-222 [Conf]
  32. Xuejun Liang, Qutaibah M. Malluhi
    Combinatorial Optimization in Mapping Generalized Template Matching onto Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:223-226 [Conf]
  33. Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki Murakami, Hamid Noori
    GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:227-230 [Conf]
  34. Fei Wang, Jack S. N. Jean
    Architectural Support for Runtime 2D Partial Reconfiguration. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:231-236 [Conf]
  35. Minoru Watanabe, Fuminori Kobayashi
    Logic Synthesis and Place-and-Route Environment for ORGAs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:237-238 [Conf]
  36. Minoru Watanabe, Fuminori Kobayashi
    Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:239-240 [Conf]
  37. Vinay Sriram, David Kearney
    A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:241-243 [Conf]
  38. Vinay Sriram, David Kearney
    An Area Time Efficient Field Programmable Mersenne Twister Uniform Random Number Generator. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:244-246 [Conf]
  39. Janardhan Singaraju, John A. Chandy
    A Generic Lookup Cache Architecture for Network Processing Applications. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:247-248 [Conf]
  40. Giovanni Agosta, Francesco Bruschi, Marco D. Santambrogio, Donatella Sciuto
    Synthesis of Object Oriented Models on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:249-250 [Conf]
  41. Alireza Sarvi, Jenny Fan, Reto Stamm
    A Dual Configuration BIST-Based Modular Diagnostic Methodology for Embedded Cores in FPGAs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:251-252 [Conf]
  42. Heng Tan, Ronald F. DeMara, Anuja Jayraj Thakkar, Abdel Ejnioui, Jason Sattler
    Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:253-256 [Conf]
  43. Paul M. Heysters
    The Era of Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:257-264 [Conf]
  44. Steven Smith
    Dynamic Scheduling and Resource Management in Heterogeneous Computing Environments with Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:265-271 [Conf]
  45. Paul M. Heysters
    Coarse-Grained Reconfigurable Computing for Power Aware Applications. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:272-0 [Conf]
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