Conferences in DBLP
Chris Rowen The Reinvention of the Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Rowen Using configurable processors for high-efficiency multiple-processor systems. [Citation Graph (0, 0)][DBLP ] Conf ] Maya Gokhale , Christopher Rickett , Justin L. Tripp , Chung Hsu , Ronald Scrofano Promises and Pitfalls of Reconfigurable Supercomputing. [Citation Graph (0, 0)][DBLP ] Conf ] David L. Andrews , Ron Sass , Erik Anderson , Jason Agron , Wesley Peck , Jim Stevens , Fabrice Baijot , Ed Komp The Case for High Level Programming Models for Reconfigurable Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Holland , James Greco , Ian A. Troxel , Gabe Barfield , Vikas Aggarwal , Alan D. George Compile- and Run-Time Services for Distributed Hetergeneous Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Koch , Matthiaas Koerber , Jürgen Teich Searching RC5-Keys with Distributed Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Vincent Nollet , Prabhat Avasare , Diederik Verkest , Henk Corporaal Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment. [Citation Graph (0, 0)][DBLP ] Conf ] Rajarshi Mukherjee , Somsubhra Mondal , Seda Ogrenci Memik A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead. [Citation Graph (0, 0)][DBLP ] Conf ] Carlo Amicucci , Fabrizio Ferrandi , Marco D. Santambrogio , Donatella Sciuto SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Koester , Heiko Kalte , Mario Porrmann Relocation and Defragmentation for Heterogeneous Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastian Lange , Martin Middendorf Cache Architectures for Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Yvan Eustache , Jean-Philippe Diguet , Milad El Khodary RTOS-Based Hardware Software Communications and Configuration Management in the Context of a Smart Camera. [Citation Graph (0, 0)][DBLP ] Conf ] Craig Ulmer , Adrian Javelo Floating-Point Unit Reuse in an FPGA Implementation of a Ray-Triangle Intersection Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Cao Liang , Jing Ma , Xin-Ming Huang An FPGA based Co-Design Architecture for MIMO Lattice Decoders. [Citation Graph (0, 0)][DBLP ] Conf ] Gerard K. Rauwerda , Gerard J. M. Smit , Casper R. W. van Benthem , Paul M. Heysters Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Yuanqing Guo , Cornelis Hoede , Gerard J. M. Smit A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] José Delgado-Frias, Jonathan Larson, Mitchell Myjak: Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Daihan Wang , Hiroki Matsutani , Masato Yoshimi , Michihiro Koibuchi , Hideharu Amano A Parametric Study of Scalable Interconnects on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Chuan He , Guan Qin , Mi Lu , Wei Zhao Group-Alignment based Accurate Floating-Point Summation on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Volodymyr V. Kindratenko Code Partitioning for Reconfigurable High-Performance Computing: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Jeoong Sung Park , Hong-Jip Jung , Viktor K. Prasanna Efficient FPGA-based Implementations of the MIMO-OFDM Physical Layer. [Citation Graph (0, 0)][DBLP ] Conf ] Herwin Chan , Patrick Schaumont , Ingrid Verbauwhede Process Isolation for Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Marcel van de Burgwal , Gerard J. M. Smit , Gerard K. Rauwerda , Paul M. Heysters Hydra: An Energy-efficient and Reconfigurable Network Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammad Akhtar Khan , Abdul Hameed , Ahmet T. Erdogan Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC). [Citation Graph (0, 0)][DBLP ] Conf ] Chun Hok Ho , Ka Fai Cedric Yiu , Jiaquan Huo , Sven Nordholm , Wayne Luk Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation. [Citation Graph (0, 0)][DBLP ] Conf ] Joshua Noseworthy , Miriam Leeser Efficient Use of Communications Between an FPGAs Embedded Processor and its Reconfigurable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Minoru Watanabe , Mototsugu Miyano , Fuminori Kobayashi Differential Reconfiguration Architecture suitable for a Holographic Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Ryan Glabb , Laurent Imbert , Graham A. Jullien , Arnaud Tisserand , Nicolas Veyrat-Charvillon Multi-Mode Operator for SHA-2 Hash Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Saumil Merchant , Gregory D. Peterson , Seong Kong Intrinsic Embedded Hardware Evolution of Block-based Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Bi , Gregory D. Peterson , G. Lee Warren , Robert J. Harrison Hardware Acceleration of Parallel Lagged-Fibonacci Pseudo Random Number Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Samie , Gabriel Dragffy , Ebrahim Farjah Metamorphic Memory Based Bio-Inspired Reconfigurable Celluar Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Xuejun Liang , Qutaibah M. Malluhi Combinatorial Optimization in Mapping Generalized Template Matching onto Reconfigurable Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Farhad Mehdipour , Morteza Saheb Zamani , Mehdi Sedighi , Kazuaki Murakami , Hamid Noori GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Wang , Jack S. N. Jean Architectural Support for Runtime 2D Partial Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Minoru Watanabe , Fuminori Kobayashi Logic Synthesis and Place-and-Route Environment for ORGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Minoru Watanabe , Fuminori Kobayashi Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array. [Citation Graph (0, 0)][DBLP ] Conf ] Vinay Sriram , David Kearney A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System. [Citation Graph (0, 0)][DBLP ] Conf ] Vinay Sriram , David Kearney An Area Time Efficient Field Programmable Mersenne Twister Uniform Random Number Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Janardhan Singaraju , John A. Chandy A Generic Lookup Cache Architecture for Network Processing Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Giovanni Agosta , Francesco Bruschi , Marco D. Santambrogio , Donatella Sciuto Synthesis of Object Oriented Models on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Alireza Sarvi , Jenny Fan , Reto Stamm A Dual Configuration BIST-Based Modular Diagnostic Methodology for Embedded Cores in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Heng Tan , Ronald F. DeMara , Anuja Jayraj Thakkar , Abdel Ejnioui , Jason Sattler Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Paul M. Heysters The Era of Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Smith Dynamic Scheduling and Resource Management in Heterogeneous Computing Environments with Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Paul M. Heysters Coarse-Grained Reconfigurable Computing for Power Aware Applications. [Citation Graph (0, 0)][DBLP ] Conf ] 