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Publications of Author

1. Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle
   Hardware Implementation of an Elliptic Curve Processor over GF(p). [Citation Graph (0, 0)][DBLP]
   ASAP, 2003, pp:433-443 [Conf]
   
2. Siddika Berna Örs, Elisabeth Oswald, Bart Preneel
   Power-Analysis Attacks on an FPGA - First Experimental Results. [Citation Graph (0, 0)][DBLP]
   CHES, 2003, pp:35-50 [Conf]
   
3. François-Xavier Standaert, Siddika Berna Örs, Bart Preneel
   Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure? [Citation Graph (0, 0)][DBLP]
   CHES, 2004, pp:30-44 [Conf]
   
4. Lejla Batina, Geeke Bruin-Muurling, Siddika Berna Örs
   Flexible Hardware Design for RSA and Elliptic Curve Cryptosystems. [Citation Graph (0, 0)][DBLP]
   CT-RSA, 2004, pp:250-263 [Conf]
   
5. Siddika Berna Örs, Ahmet Dervisoglu
   Modeling Bit Multiplication Blocks for DSP Applications Using VHDL. [Citation Graph (0, 0)][DBLP]
   EUROMICRO, 1999, pp:1402-1405 [Conf]
   
6. François-Xavier Standaert, Siddika Berna Örs, Jean-Jacques Quisquater, Bart Preneel
   Power Analysis Attacks Against FPGA Implementations of the DES. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:84-94 [Conf]
   
7. Nele Mentens, Siddika Berna Örs, Bart Preneel
   An FPGA implementation of an elliptic curve processor GF(2^m). [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2004, pp:454-457 [Conf]
   
8. Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle
   Hardware Implementation of a Montgomery Modular Multiplier in a Systolic Array. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2003, pp:184- [Conf]
   
9. Siddika Berna Örs, Frank K. Gürkaynak, Elisabeth Oswald, Bart Preneel
   Power-Analysis Attack on an ASIC AES implementation. [Citation Graph (0, 0)][DBLP]
   ITCC (2), 2004, pp:546-552 [Conf]
   
10. Nele Mentens, Siddika Berna Örs, Bart Preneel, Joos Vandewalle
    An FPGA Implementation of a Montgomery Multiplier Over GF(2^m). [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
    
11. Lejla Batina, Siddika Berna Örs, Bart Preneel, Joos Vandewalle
    Hardware architectures for public key cryptography. [Citation Graph (0, 0)][DBLP]
    Integration, 2003, v:34, n:1-2, pp:1-64 [Journal]
    
12. Elke De Mulder, Siddika Berna Örs, Bart Preneel, Ingrid Verbauwhede
    Differential power and electromagnetic attacks on a FPGA implementation of elliptic curve cryptosystems. [Citation Graph (0, 0)][DBLP]
    Computers & Electrical Engineering, 2007, v:33, n:5-6, pp:367-382 [Journal]
    
13. 
    Low-cost implementations of NTRU for pervasive security. [Citation Graph (, )][DBLP]
    
    
14. 
    Differential Power Analysis resistant hardware implementation of the RSA cryptosystem. [Citation Graph (, )][DBLP]