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Publications of Author

1. Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata
   An arbitrary chaos generator core curcuit using PWM/PPM signals. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:23-24 [Conf]
   
2. Makoto Nagata, Youichi Nishimori, Takashi Morie, Atsushi Iwata, Yoshitaka Murasaka
   Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2002, pp:71-76 [Conf]
   
3. Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata
   Test circuits for substrate noise evaluation in CMOS digital ICs. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2001, pp:13-14 [Conf]
   
4. Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata
   A smart imager for the vision processing front-END. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:19-20 [Conf]
   
5. Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata
   A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. [Citation Graph (0, 0)][DBLP]
   ICNC (3), 2005, pp:1006-1014 [Conf]
   
6. Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata
   Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. [Citation Graph (0, 0)][DBLP]
   ICONIP, 1998, pp:586-589 [Conf]
   
7. Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata
   Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. [Citation Graph (0, 0)][DBLP]
   ICONIP, 1998, pp:582-585 [Conf]
   
8. Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie
   A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. [Citation Graph (0, 0)][DBLP]
   VLSI, 1999, pp:77-88 [Conf]
   
9. YoungJae Kim, Takashi Morie
   A pixel-parallel anisotropic diffusion algorithm for subjective contour generation. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2005, pp:4237-4240 [Conf]
   
10. Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata
    Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:482-487 [Conf]
    
11. Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
    A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. [Citation Graph (0, 0)][DBLP]
    KES, 2003, pp:169-176 [Conf]
    
12. Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata
    A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. [Citation Graph (0, 0)][DBLP]
    KES, 2004, pp:995-1001 [Conf]
    
13. Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata
    An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. [Citation Graph (0, 0)][DBLP]
    NIPS, 2001, pp:1115-1122 [Conf]
    
14. Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata
    Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:71-76 [Conf]
    
15. Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
    A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture. [Citation Graph (0, 0)][DBLP]
    Journal of Intelligent and Fuzzy Systems, 2004, v:15, n:3-4, pp:173-179 [Journal]
    
16. Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata
    Measurements and analyses of substrate noise waveform inmixed-signal IC environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:6, pp:671-678 [Journal]
    
17. 
    Design methods for pipeline & delta-sigma A-to-D converters with convex optimization. [Citation Graph (, )][DBLP]
    
    
18. 
    An FPGA-based CollisionWarning System Using Hybrid Approach. [Citation Graph (, )][DBLP]
    
    
19. 
    Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach. [Citation Graph (, )][DBLP]
    
    
20. 
    CMOS pulse-modulation circuit implementation of phase-locked loop neural networks. [Citation Graph (, )][DBLP]
    
    
21. 
    Video Monitoring of Slope Failure Using Spatiotemporal Gabor Filtering. [Citation Graph (, )][DBLP]
    
    
22. 
    A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Driven by Quantized Nonlinear Waveforms. [Citation Graph (, )][DBLP]
    
    
23. 
    A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. [Citation Graph (, )][DBLP]