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Publications of Author

1. Fabrizio Ferrandi, G. Ferrara, R. Palazzo, Vincenzo Rana, Marco D. Santambrogio
   VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2006, pp:- [Conf]
   
2. Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Boris Kettelhoit, Markus Köster, Mario Porrmann, Ulrich Rückert
   Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2007, pp:1-8 [Conf]
   
3. Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto
   Dynamic Reconfigurability in Embedded System Design. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:2734-2737 [Conf]
   
4. Matteo Murgida, Alessandro Panella, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto
   Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2006, pp:74-79 [Conf]
   
5. 
   The Shining embedded system design methodology based on self dynamic reconfigurable architectures. [Citation Graph (, )][DBLP]
   
   
6. 
   Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems. [Citation Graph (, )][DBLP]
   
   
7. 
   A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow. [Citation Graph (, )][DBLP]
   
   
8. 
   A Generation Flow for Self-Reconfiguration Controllers Customization. [Citation Graph (, )][DBLP]
   
   
9. 
   Low cost smartcams design. [Citation Graph (, )][DBLP]
   
   
10. 
    An architecture for dynamically reconfigurable real time audio processing systems. [Citation Graph (, )][DBLP]
    
    
11. 
    Operating system support for online partial dynamic reconfiguration management. [Citation Graph (, )][DBLP]
    
    
12. 
    Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices. [Citation Graph (, )][DBLP]
    
    
13. 
    A novel design framework for the design of reconfigurable systems based on NoCs. [Citation Graph (, )][DBLP]
    
    
14. 
    A novel SoC design methodology combining adaptive software and reconfigurable hardware. [Citation Graph (, )][DBLP]
    
    
15. 
    HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures. [Citation Graph (, )][DBLP]
    
    
16. 
    On-line task management for a reconfigurable cryptographic architecture. [Citation Graph (, )][DBLP]
    
    
17. 
    A light-weight Network-on-Chip architecture for dynamically reconfigurable systems. [Citation Graph (, )][DBLP]
    
    
18. 
    An adaptive genetic algorithm for dynamically reconfigurable modules allocation. [Citation Graph (, )][DBLP]
    
    
19. 
    A Requirements-Driven Simulation Framework for Communication Infrastructures Design. [Citation Graph (, )][DBLP]