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Shahrzad Mirkhani: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi
    Fault Simulation for VHDL Based Test Bench and BIST Evaluation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:396-0 [Conf]
  2. Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi
    Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:374-0 [Conf]
  3. Shahrzad Mirkhani, Zainalabedin Navabi
    Enhancing Fault Simulation Performance by Dynamic Fault Clustering. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:278-283 [Conf]
  4. Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi
    Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:823- [Conf]
  5. Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi
    RT level reliability enhancement by constructing dynamic TMRS. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:172-175 [Conf]

  6. A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library. [Citation Graph (, )][DBLP]


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