Conferences in DBLP
Yun Shao , Irith Pomeranz , Sudhakar M. Reddy On Generating High Quality Tests for Transition Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Ilia Polian , Irith Pomeranz , Bernd Becker Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Shiyi Xu , Jianwen Chen Maximum Distance Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Junichi Hirase High Precision Result Evaluation of VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-ling Yang , Oliver Chiu-sing Choy , Cheong-fat Chan , Kong-Pong Pun A Totally Self-Checking Dynamic Asynchronous Datapath. [Citation Graph (0, 0)][DBLP ] Conf ] Petros Drineas , Yiorgos Makris Non-Intrusive Design of Concurrently Self-Testable FSMs. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir , Zhen Guo Test Limitations of Parametric Faults in Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Ishida , Takahiro J. Yamaguchi , Mani Soma , Hirobumi Musha Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Hao-Chiao Hong , Jiun-Lang Huang , Kwang-Ting Cheng , Cheng-Wen Wu On-chip Analog Response Extraction with 1-Bit ? - Modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinori Hosokawa , Hiroshi Date , Michiaki Muraoka A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences. [Citation Graph (0, 0)][DBLP ] Conf ] Seiji Kajihara , Kenjiro Taniguchi , Kohei Miyase , Irith Pomeranz , Sudhakar M. Reddy Test Data Compression Using Don?t-Care Identification and Statistical Encoding. [Citation Graph (0, 0)][DBLP ] Conf ] Atlaf Ul Amin , Satoshi Ohtake , Hideo Fujiwara Design for Two-Pattern Testability of Controller-Data Path Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Takaki Yoshida , Masafumi Watari MD-SCAN Method for Low Power Scan Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Xiang , Shan Gu , Hideo Fujiwara Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Benso , Stefano Di Carlo , Giorgio Di Natale , Paolo Prinetto Specification and Design of a New Memory Fault Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Zaid Al-Ars , A. J. van de Goor DRAM Specific Approximation of the Faulty Behavior of Cell Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Shu-Rong Lee , Ming-Jun Hsiao , Tsin-Yuan Chang An Access Timing Measurement Unit of Embedded Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Lihong Tong , Kazuki Suzuki , Hideo Ito Optimal Seed Generation for Delay Fault Detection BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Octavian Petre , Hans G. Kerkhoff On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoo Inoue , Tomokazu Miura , Akio Tamura , Hideo Fujiwara A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design. [Citation Graph (0, 0)][DBLP ] Conf ] Yiorgos Makris , Alex Orailoglu Test Requirement Analysis for Low Cost Hierarchical Test Path Construction. [Citation Graph (0, 0)][DBLP ] Conf ] P. Zhongliang Testable Realizations for ESOP Expressions of Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Hong-Sik Kim , Sungho Kang DPSC SRAM Transparent Test Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Xuemei Zhao , Yizheng Yu , Chunxu Chen Tests for Word-Oriented Content Addressable Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Swarup Bhunia , Hai Li , Kaushik Roy A High Performance IDDQ Testable Cache for Scaled CMOS Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Wichian Sirisaengtaksin , Sandeep K. Gupta Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology. [Citation Graph (0, 0)][DBLP ] Conf ] Ming Shae Wu , Chung-Len Lee , Chi Peng Chang , Jwu E. Chen A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuya Shimizu , Noriyoshi Itazaki , Kozo Kinoshita Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Marong Phadoongsidhi , Kim T. Le , Kewal K. Saluja A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Santanu Chattopadhyay Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Emil Gizdarski , Hideo Fujiwara Fault Set Partition for Efficient Width Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Nan-Cheng Li , Sying-Jyan Wang A Reseeding Technique for LFSR-Based BIST Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Emmanouil Kalligeros , Xrysovalantis Kavousianos , Dimitris Nikolos A ROMless LFSR Reseeding Scheme for Scan-based BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Min-Kyu Joo , Jin-Hyung Kim , Yoon-Hwa Choi A Fault-Tolerant Architecture for Symmetric Block Ciphers. [Citation Graph (0, 0)][DBLP ] Conf ] Fabian Vargas , Djones Lettnin , Diogo B. Brum , Dárcio Prestes A New Learning Approach to Design Fault Tolerant ANNs: Finally a Zero HW-SW Overhead. [Citation Graph (0, 0)][DBLP ] Conf ] Fabian Vargas , Rubem Dutra R. Fagundes , Daniel Barros Jr. Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Shyue-Kung Lu , Chien-Hung Yeh Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Shyue-Kung Lu , Chung-Yang Chen Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's. [Citation Graph (0, 0)][DBLP ] Conf ] Keith J. Keller , Hiroshi Takahashi , Kim T. Le , Kewal K. Saluja , Yuzo Takamatsu Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Shi-Yu Huang Diagnosis Of Byzantine Open-Segment Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Alexej Dmitriev , Michael Gössel , Krishnendu Chakrabarty Robust Space Compaction of Test Responses. [Citation Graph (0, 0)][DBLP ] Conf ] Niloy Ganguly , Anindyasundar Nandi , Sukanta Das , Biplab K. Sikdar , Parimal Pal Chaudhuri An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS). [Citation Graph (0, 0)][DBLP ] Conf ] Sheng-Hung Hsieh , Ming-Jun Hsiao , Tsin-Yuan Chang An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Sousuke Amasaki , Takashi Yoshitomi , Osamu Mizuno , Tohru Kikuno , Yasunari Takagi Statistical Analysis of Time Series Data on the Number of Faults Detected by Statistical Analysis of Time Series Data on the Number of Faults Detected by Software Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Cherng Lin , Szu-Wen Lin An Analytic Software Testability Model. [Citation Graph (0, 0)][DBLP ] Conf ] Juichi Takahashi , Yoshiaki Kakuda Effective Automated Testing: A Solution of Graphical Object Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Kazumi Hatayama , Michinobu Nakao , Yasuo Sato At-Speed Built-in Test for Logic Circuits with Multiple Clocks. [Citation Graph (0, 0)][DBLP ] Conf ] Masayoshi Yoshimura , Toshinori Hosokawa , Mitsuyasu Ohta A Test Point Insertion Method to Reduce the Number of Test Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Date , Toshinori Hosokawa , Michiaki Muraoka A SoC Test Strategy Based on a Non-Scan DFT Method. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuhiko Iijima , Armagan Akar , Charlie McDonald , Dwayne Burek Embedded Test Solution as a Breakthrough in Reducing Cost of Test for System on Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Rohit Kapur , Thomas W. Williams Manufacturing Test of SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Vikram Iyengar , Krishnendu Chakrabarty , Erik Jan Marinissen Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Shin-ya Kobayashi , Yuzo Takamatsu A Method to Reduce Power Dissipation during Test for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zuying Luo , Xiaowei Li , Huawei Li , Shiyuan Yang , Yinghua Min Test Power Optimization Techniques for CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen-Jong Lee , Jih-Jeen Chen Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling. [Citation Graph (0, 0)][DBLP ] Conf ] Jaehoon Song , Sungju Park A Simple Wrapped Core Linking Module for SoC Test Access. [Citation Graph (0, 0)][DBLP ] Conf ] K. Y. Ko , Mike W. T. Wong , Y. S. Lee Testing System-On-Chip by Summations of Cores? Test Output Voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Wea Wang , Jing-Reng Huang , Yen-Fu Lin , Kuo-Liang Cheng , Chih-Tsun Huang , Cheng-Wen Wu , Youn-Long Lin Test Scheduling of BISTed Memory Cores for SOC. [Citation Graph (0, 0)][DBLP ] Conf ] Tai-Ying Jiang , Chien-Nan Jimmy Liu , Jing-Yang Jou Effective Error Diagnosis for RTL Designs in HDLs. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Gianluca Cumani , Matteo Sonza Reorda , Giovanni Squillero Evolutionary Test Program Induction for Microprocessor Design Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Shahrzad Mirkhani , Meisam Lavasani , Zainalabedin Navabi Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. [Citation Graph (0, 0)][DBLP ] Conf ] Harald J. Zainzinger Testing Embedded Systems by Using a C++ Script Interpreter. [Citation Graph (0, 0)][DBLP ] Conf ] Rochit Rajsuman Extending EDA Environment From Design to Test. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuhiro Yamada , Yoshikazu Takahashi Vector Memory Expansion System For T33xx Logic Tester. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Larsson , Klas Arvidsson , Hideo Fujiwara , Zebo Peng Integrated Test Scheduling, Test Parallelization and TAMDesign. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Huang , Sudhakar M. Reddy , Wu-Tung Cheng Core - Clustering Based SOC Test Scheduling Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Huan-Shan Hsu , Jing-Reng Huang , Kuo-Liang Cheng , Chih-Wea Wang , Chih-Tsun Huang , Cheng-Wen Wu , Youn-Long Lin Test Scheduling and Test Access Architecture Optimization for System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Michinishi , Tokumi Yokohira , Takuji Okamoto , Toshifumi Kobayashi , Tsutomu Hondo CMOS Floating Gate Defect Detection Using I DDQ Test with DC Power Supply. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Yotsuyanagi , Masaki Hashizume , Takeomi Tamesada Test Time Reduction for I DDQ Testing by Arranging Test Vectors. [Citation Graph (0, 0)][DBLP ] Conf ] Shambhu J. Upadhyaya , Jae Min Lee , Padmanabhan Nair Time Slot Specification Based Approach to Analog Fault Diagnosis Using Built-in Current Sensors and Test Point Insertion. [Citation Graph (0, 0)][DBLP ] Conf ] 