The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Daniel Etiemble: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lionel Lacassagne, Daniel Etiemble, S. A. Ould Kablia
    16-bit Floating Point Instructions for Embedded Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    CAMP, 2005, pp:198-203 [Conf]
  2. Daniel Etiemble, Samir Bouaziz, Lionel Lacassagne
    Customizing 16-bit FP Instructions on a NIOS II Processor for FPGA Image and Media Processing. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:61-66 [Conf]
  3. P. Bosch, A. Carloganu, Daniel Etiemble
    Complete x86 instruction trace generation from hardware bus collect. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:402-408 [Conf]
  4. A. Pavlov, Jean-Luc Béchennec, Daniel Etiemble
    Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:409-0 [Conf]
  5. Franck Cappello, Olivier Richard, Daniel Etiemble
    Investigating the Performance of Two Programming Models for Clusters of SMP PCs. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:349-359 [Conf]
  6. Franck Cappello, Jean-Luc Béchennec, Franck Delaplace, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble
    Balanced Distributed Memory Parallel Computers. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:72-76 [Conf]
  7. Daniel Etiemble, Lionel Lacassagne
    16-Bit FP Sub-Word Parallelism to Facilitate Compiler Vectorization and Improve Performance of Image and Media Processing. [Citation Graph (0, 0)][DBLP]
    ICPP, 2004, pp:540-547 [Conf]
  8. Daniel Etiemble
    On the Performance of Multivalued Integrated Circuits: Past, Present and Future. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:156-164 [Conf]
  9. Daniel Etiemble, C. Chanussot, Vincent Néri
    4-Valued BiCMOS Circuits for the Transmission System of a Massively Parallel Architecture. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1990, pp:348-354 [Conf]
  10. Daniel Etiemble, K. Navi
    A Basis for the Comparison of Binary and m-Valued Current Mode Circuits: the Multioperand Addition with Redundant Number Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:216-221 [Conf]
  11. A. Kazeminejad, K. Navi, Daniel Etiemble
    CML Current Mode Full Adders for 2.5-V Power Supply. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:10-14 [Conf]
  12. K. Navi, Daniel Etiemble
    From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:58-63 [Conf]
  13. K. Navi, A. Kazeminejad, Daniel Etiemble
    Performance of CMOS Current Mode Full Adders. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:27-34 [Conf]
  14. Pascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec, He Hé
    The Database Processor 'RAPID'. [Citation Graph (0, 0)][DBLP]
    IWDM, 1987, pp:171-187 [Conf]
  15. Daniel Etiemble, Cécile Germain
    Standard Microprocessors Versus Custom Processing Elements for Massively Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    PaCT, 1995, pp:320-325 [Conf]
  16. Cécile Germain, Jacques Laminie, M. Pallud, Daniel Etiemble
    An HPF Case Study of a Domain-Decomposition Based Irregular Application. [Citation Graph (0, 0)][DBLP]
    PaCT, 1997, pp:201-209 [Conf]
  17. Franck Cappello, Daniel Etiemble
    Communications in Parallel Architectures and Networks of Workstations: From Standardisation to New Standards. [Citation Graph (0, 0)][DBLP]
    PaCT, 1997, pp:298-310 [Conf]
  18. Franck Cappello, Olivier Richard, Daniel Etiemble
    Performance of the NAS Benchmarks on a Cluster of SMP PCs Using a Parallelization of the MPI Programs with OpenMP. [Citation Graph (0, 0)][DBLP]
    PaCT, 1999, pp:339-350 [Conf]
  19. F. Capello, Jean-Luc Béchennec, Franck Delaplace, Damien Gautier de Lahaut, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble
    A Parralel Architecture Based on Compiled Communication Schemes. [Citation Graph (0, 0)][DBLP]
    PARCO, 1993, pp:371-378 [Conf]
  20. Franck Cappello, Olivier Richard, Daniel Etiemble
    Performance Evaluation of Two Programming Models for a Cluster of PC Biprocessors. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:1912-1918 [Conf]
  21. Franck Cappello, Daniel Etiemble
    MPI versus MPI+OpenMP on IBM SP for the NAS Benchmarks. [Citation Graph (0, 0)][DBLP]
    SC, 2000, pp:- [Conf]
  22. Daniel Etiemble, Michel Israël
    Comparison of Binary and Multivalued ICs According to VLSI Criteria. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1988, v:21, n:4, pp:28-42 [Journal]
  23. Cécile Germain, Jean-Luc Béchennec, Daniel Etiemble, Jean-Paul Sansonnet
    A Communication Architecture for a Massively Parallel Message-Passing Multicomputer. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1993, v:19, n:4, pp:338-348 [Journal]
  24. Daniel Etiemble
    Multivalued I2L Circuits for TSC Checkers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:6, pp:537-540 [Journal]
  25. Daniel Etiemble, Michel Israël
    Implementation of Ternary Circuits with Binary Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:12, pp:1222-1233 [Journal]
  26. Daniel Etiemble
    Computer arithmetic and hardware: "off the shelf" microprocessors versus "custom hardware". [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2002, v:279, n:1-2, pp:3-27 [Journal]
  27. Franck Cappello, Daniel Etiemble
    MPI ou MPI+OpenMP sur grappes de multiprocesseurs? [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2002, v:21, n:2, pp:253-272 [Journal]
  28. Franck Cappello, Olivier Richard, Daniel Etiemble
    Understanding performance of SMP clusters running MPI programs. [Citation Graph (0, 0)][DBLP]
    Future Generation Comp. Syst., 2001, v:17, n:6, pp:711-720 [Journal]

  29. Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor. [Citation Graph (, )][DBLP]


  30. Algorithms and multi-valued circuits for the multioperand addition in the binary stored-carry number system. [Citation Graph (, )][DBLP]


Search in 0.038secs, Finished in 0.041secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002