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Pierre Michaud: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pierre Michaud, André Seznec, Stéphan Jourdan
    Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:2-10 [Conf]
  2. André Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud
    Multiple-Block Ahead Branch Predictors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1996, pp:116-127 [Conf]
  3. Pierre Michaud
    Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:186-197 [Conf]
  4. Pierre Michaud, André Seznec
    Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:27-36 [Conf]
  5. Pierre Michaud, André Seznec, Richard Uhlig
    Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:292-303 [Conf]
  6. Pierre Michaud
    A statistical model of skewed-associativity. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2003, pp:204-213 [Conf]
  7. Pierre Michaud, Christian Saguez
    A Learning Grid for the multichallenge school ECP. [Citation Graph (0, 0)][DBLP]
    LeGE-WG 1, 2002, pp:- [Conf]
  8. Pierre Michaud, André Seznec, Stéphan Jourdan
    An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2001, v:29, n:1, pp:35-58 [Journal]
  9. Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, André Seznec
    Performance implications of single thread migration on a chip multi-core. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:4, pp:80-91 [Journal]
  10. Pierre Michaud, André Seznec, Damien Fetis, Yiannakis Sazeides, Theofanis Constantinou
    A study of thread migration in temperature-constrained multicores. [Citation Graph (0, 0)][DBLP]
    TACO, 2007, v:4, n:2, pp:- [Journal]

  11. Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. [Citation Graph (, )][DBLP]


  12. Online compression of cache-filtered address traces. [Citation Graph (, )][DBLP]


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