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André Seznec: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pierre Michaud, André Seznec, Stéphan Jourdan
    Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:2-10 [Conf]
  2. D. N. Truong, François Bodin, André Seznec
    Improving Cache Behavior of Dynamically Allocated Data Structures. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:322-0 [Conf]
  3. André Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud
    Multiple-Block Ahead Branch Predictors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1996, pp:116-127 [Conf]
  4. Bas Aarts, Michel Barreteau, François Bodin, Peter Brinkhaus, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Peter M. W. Knijnenburg, Michael F. P. O'Boyle, Erven Rohou, Rizos Sakellariou, Henk Schepers, André Seznec, Elena Stöhr, Marco Verhoeven, Harry A. G. Wijshoff
    OCEANS: Optimizing Compilers for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1997, pp:1351-1356 [Conf]
  5. Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec
    Topic 08+13: Instruction-Level Parallelism and Computer Architecture. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:385- [Conf]
  6. Michel Barreteau, François Bodin, Peter Brinkhaus, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Peter M. W. Knijnenburg, Michael F. P. O'Boyle, Erven Rohou, Rizos Sakellariou, André Seznec, Elena Stöhr, Menno Treffers, Harry A. G. Wijshoff
    OCEANS: Optimising Compilers for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1998, pp:1123-1130 [Conf]
  7. Michel Barreteau, François Bodin, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Toru Kisuki, Peter M. W. Knijnenburg, Paul van der Mark, Andy Nisbet, Michael F. P. O'Boyle, Erven Rohou, André Seznec, Elena Stöhr, Menno Treffers, Harry A. G. Wijshoff
    OCEANS - Optimising Compilers for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:1171-1175 [Conf]
  8. Kemal Ebcioglu, Wolfgang Karl, André Seznec, Marco Aldinucci
    Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:506- [Conf]
  9. Thierry Lafage, André Seznec
    Combining Light Static Code Annotation and Instruction-Set Emulation for Flexible and Efficient On-the-Fly Simulation (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:178-182 [Conf]
  10. Thierry Lafage, André Seznec, Erven Rohou, François Bodin
    Code Cloning Tracing: A ``Pay per Trace'' Approach. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:1265-1268 [Conf]
  11. Sébastien Hily, André Seznec
    Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:64-0 [Conf]
  12. André Seznec
    DASC Cache. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:134-143 [Conf]
  13. Pierre Michaud, André Seznec
    Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:27-36 [Conf]
  14. André Seznec
    About Set and Skewed Associativity on Second-Level Caches. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:40-43 [Conf]
  15. Julio César Hernández Castro, José María Sierra, André Seznec
    The SAC Test: A New Randomness Test, with Some Applications to PRNG Analysis. [Citation Graph (0, 0)][DBLP]
    ICCSA (1), 2004, pp:960-967 [Conf]
  16. Nathalie Drach, André Seznec
    Semi-Unified Caches. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:25-28 [Conf]
  17. Yvon Jégou, André Seznec
    Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:487-494 [Conf]
  18. André Seznec, Yvon Jégou
    Optimizing Memory Throughput In a Tightly Coupled Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:344-346 [Conf]
  19. Yvon Jégou, André Seznec
    A asynchronous buffering network for tightly coupled multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICS, 1989, pp:331-340 [Conf]
  20. André Seznec, Yvon Jégou
    Towards a large number of pipeline processors in a tightly coupled multiprocessor using no cache. [Citation Graph (0, 0)][DBLP]
    ICS, 1988, pp:611-620 [Conf]
  21. Kun Luo, Manoj Franklin, Shubhendu S. Mukherjee, André Seznec
    Boosting SMT Performance by Speculation Control. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:2- [Conf]
  22. François Bodin, André Seznec
    Skewed Associativity Enhances Performance Predictability. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:265-274 [Conf]
  23. Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec
    Tarantula: A Vector Extension to the Alpha Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:281-0 [Conf]
  24. Pierre Michaud, André Seznec, Richard Uhlig
    Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:292-303 [Conf]
  25. André Seznec
    Analysis of the O-GEometric History Length Branch Predictor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:394-405 [Conf]
  26. André Seznec
    An Efficient Routing Control Unit for the SIGMA Network E(4). [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:158-168 [Conf]
  27. André Seznec
    A Case for Two-Way Skewed-Associative Caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:169-178 [Conf]
  28. André Seznec
    Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:384-393 [Conf]
  29. André Seznec
    Don't Use the Page Number, But a Pointer To It. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:104-113 [Conf]
  30. André Seznec, Antony Fraboulet
    Effective ahead Pipelining of Instruction Block Address Generation. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:241-252 [Conf]
  31. André Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides
    Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:295-306 [Conf]
  32. André Seznec, Yvon Jégou
    Synchronizing Processors Through Memory Requests in a Tightly Coupled Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:393-400 [Conf]
  33. André Seznec, Jacques Lenfant
    Interleaved Parallel Schemes: Improving Memory Throughput on Supercomputers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:246-255 [Conf]
  34. André Seznec, Jacques Lenfant
    Odd Memory Systems May be Quite Interesting. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:341-350 [Conf]
  35. Gilles Pokam, Olivier Rochecouste, André Seznec, François Bodin
    Speculative software management of datapath-width for energy optimization. [Citation Graph (0, 0)][DBLP]
    LCTES, 2004, pp:78-87 [Conf]
  36. Nathalie Drach, André Seznec
    MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:193-201 [Conf]
  37. André Seznec, Karl Courtel
    Controlling and sequencing a heavily pipelined floating-point operator. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:111-114 [Conf]
  38. André Seznec, Eric Toullec, Olivier Rochecouste
    Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:383-394 [Conf]
  39. André Seznec, François Bodin
    Skewed-associative Caches. [Citation Graph (0, 0)][DBLP]
    PARLE, 1993, pp:304-316 [Conf]
  40. Amaury Darsch, André Seznec
    IATO: A Flexible EPIC Simulation Environment. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2004, pp:58-65 [Conf]
  41. Pierre Michaud, André Seznec, Stéphan Jourdan
    An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2001, v:29, n:1, pp:35-58 [Journal]
  42. Erven Rohou, François Bodin, Christine Eisenbeis, André Seznec
    Handling Global Constraints in Compiler Strategy. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2000, v:28, n:4, pp:325-345 [Journal]
  43. Romain Dolbeau, André Seznec
    CASH: Revisiting Hardware Sharing in Single-Chip Parallel Processors. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2004, v:6, n:, pp:- [Journal]
  44. Yvon Jégou, André Seznec
    Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1986, v:3, n:4, pp:508-526 [Journal]
  45. André Seznec, Jacques Lenfant
    Odd Memory Systems: A New Approach. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:26, n:2, pp:248-256 [Journal]
  46. Nathalie Drach, Alain Gefflaut, Philippe Joubert, André Seznec
    About Cache Associativity in Low-Cost Shared Memory Multi-Microprocessors. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1995, v:5, n:, pp:475-487 [Journal]
  47. Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, André Seznec
    Performance implications of single thread migration on a chip multi-core. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:4, pp:80-91 [Journal]
  48. Olivier Rochecouste, Gilles Pokam, André Seznec
    A case for a complexity-effective, width-partitioned microarchitecture. [Citation Graph (0, 0)][DBLP]
    TACO, 2006, v:3, n:3, pp:295-326 [Journal]
  49. François Bodin, André Seznec
    Skewed Associativity Improves Program Performance and Enhances Predictability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:5, pp:530-544 [Journal]
  50. André Seznec
    Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:7, pp:924-927 [Journal]
  51. André Seznec
    A New Interconnection Network for SIMD Computers: The Sigma Network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:7, pp:794-801 [Journal]
  52. André Seznec
    Decoupled Sectored Caches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:2, pp:210-215 [Journal]
  53. André Seznec, Roger Espasa
    Conflict-Free Accesses to Strided Vectors on a Banked Cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:7, pp:913-196 [Journal]
  54. André Seznec, Nicolas Sendrier
    HAVEGE: A user-level software heuristic for generating empirically strong random numbers. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Model. Comput. Simul., 2003, v:13, n:4, pp:334-346 [Journal]
  55. André Seznec, Jacques Lenfant
    Interleaved Parallel Schemes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:12, pp:1329-1334 [Journal]
  56. Julio César Hernández Castro, José María Sierra, André Seznec, Antonio Izquierdo, Arturo Ribagorda
    The strict avalanche criterion randomness test. [Citation Graph (0, 0)][DBLP]
    Mathematics and Computers in Simulation, 2005, v:68, n:1, pp:1-7 [Journal]
  57. Thomas Piquet, Olivier Rochecouste, André Seznec
    Exploiting Single-Usage for Effective Memory Management. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:90-101 [Conf]
  58. Hans Vandierendonck, André Seznec
    Fetch Gating Control Through Speculative Instruction Window Weighting. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:120-135 [Conf]
  59. Pierre Michaud, André Seznec, Damien Fetis, Yiannakis Sazeides, Theofanis Constantinou
    A study of thread migration in temperature-constrained multicores. [Citation Graph (0, 0)][DBLP]
    TACO, 2007, v:4, n:2, pp:- [Journal]

  60. Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. [Citation Graph (, )][DBLP]


  61. Zero-content augmented caches. [Citation Graph (, )][DBLP]


  62. Parallel HAVEGE. [Citation Graph (, )][DBLP]


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