Conferences in DBLP

International Symposium on High-Performance Computer Architecture (HPCA) (hpca)
2001 (conf/hpca/2001)

1. Hsien-Hsin S. Lee, Mikhail Smelyanskiy, Chris J. Newburn, Gary S. Tyson
   Stack Value File: Custom Microarchitecture for the Stack. [Citation Graph (0, 0)][DBLP]
   HPCA, 2001, pp:5-14 [Conf]
   
2. Perry H. Wang, Hong Wang, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen
   Register Renaming and Scheduling for Dynamic Execution of Predicated Code. [Citation Graph (0, 0)][DBLP]
   HPCA, 2001, pp:15-26 [Conf]
   
3. Pierre Michaud, André Seznec
   Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors. [Citation Graph (0, 0)][DBLP]
   HPCA, 2001, pp:27-36 [Conf]
   
4. Amir Roth, Gurindar S. Sohi
   Speculative Data-Driven Multithreading. [Citation Graph (0, 0)][DBLP]
   HPCA, 2001, pp:37-0 [Conf]
   
5. Xiaogang Qiu, Michel Dubois
   Towards Virtually-Addressed Memory Hierarchies. [Citation Graph (0, 0)][DBLP]
   HPCA, 2001, pp:51-62 [Conf]
   
6. Zhen Fang, Lixin Zhang, John B. Carter, Wilson C. Hsieh, Sally A. McKee
   Reevaluating Online Superpage Promotion with Hardware Support. [Citation Graph (0, 0)][DBLP]
   HPCA, 2001, pp:63-72 [Conf]
   
7. Bülent Abali, Hubertus Franke, Xiaowei Shen, Dan E. Poff, T. Basil Smith
   Performance of Hardware Compressed Main Memory. [Citation Graph (0, 0)][DBLP]
   HPCA, 2001, pp:73-0 [Conf]
   
8. Andreas Moshovos, Gokhan Memik, Babak Falsafi, Alok N. Choudhary
   JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers. [Citation Graph (0, 0)][DBLP]
   HPCA, 2001, pp:85-96 [Conf]
   
9. Manuel E. Acacio, José González, José M. García, José Duato
   A New Scalable Directory Architecture for Large-Scale Multiprocessors. [Citation Graph (0, 0)][DBLP]
   HPCA, 2001, pp:97-106 [Conf]
   
10. Mithuna Thottethodi, Alvin R. Lebeck, Shubhendu S. Mukherjee
    Self-Tuned Congestion Control for Multiprocessor Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:107-0 [Conf]
    
11. Jaejin Lee, Yan Solihin, Josep Torrellas
    Automatically Mapping Code on an Intelligent Memory Architecture. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:121-0 [Conf]
    
12. Krishnan Kailas, Kemal Ebcioglu, Ashok K. Agrawala
    CARS: A New Code Generation Framework for Clustered ILP Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:133-0 [Conf]
    
13. Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar
    An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:147-158 [Conf]
    
14. Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin
    DRAM Energy Management Using Software and Hardware Directed Power Mode Control. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:159-170 [Conf]
    
15. David Brooks, Margaret Martonosi
    Dynamic Thermal Management for High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:171-0 [Conf]
    
16. Eric Tune, Dongning Liang, Dean M. Tullsen, Brad Calder
    Dynamic Prediction of Critical Path Instructions. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:185-196 [Conf]
    
17. Daniel A. Jiménez, Calvin Lin
    Dynamic Branch Prediction with Perceptrons. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:197-206 [Conf]
    
18. Bart Goeman, Hans Vandierendonck, Koenraad De Bosschere
    Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:207-0 [Conf]
    
19. Jesús Corbal, Roger Espasa, Mateo Valero
    DLP + TLP Processors for the Next Generation of Media Workloads. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:219-228 [Conf]
    
20. Harold W. Cain, Ravi Rajwar, Morris Marden, Mikko H. Lipasti
    An Architectural Evaluation of Java TPC-W. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:229-240 [Conf]
    
21. Craig B. Zilles, Gurindar S. Sohi
    A Programmable Co-Processor for Profiling. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:241-0 [Conf]
    
22. Li-Shiuan Peh, William J. Dally
    A Delay Model and Speculative Architecture for Pipelined Routers. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:255-266 [Conf]
    
23. Taliver Heath, Samian Kaur, Richard P. Martin, Thu D. Nguyen
    Quantifying the Impact of Architectural Scaling on Communication. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:267-0 [Conf]
    
24. Murali Annavaram, Jignesh M. Patel, Edward S. Davidson
    Call Graph Prefetching for Database Applications. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:281-0 [Conf]
    
25. Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak
    Branch History Guided Instruction Prefetching. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:291-300 [Conf]
    
26. Wi-Fen Lin, Steven K. Reinhardt, Doug Burger
    Reducing DRAM Latencies with an Integrated Memory Hierarchy Design. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:301-312 [Conf]