Journals in DBLP
Norman P. Jouppi , Rakesh Kumar , Dean M. Tullsen Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05). [Citation Graph (0, 0)][DBLP ] Journal ] James Laudon Performance/Watt: the new server focus. [Citation Graph (0, 0)][DBLP ] Journal ] John D. Davis , Cong Fu , James Laudon The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors. [Citation Graph (0, 0)][DBLP ] Journal ] Lisa R. Hsu , Ravishankar R. Iyer , Srihari Makineni , Steven K. Reinhardt , Donald Newell Exploring the cache design space for large scale CMPs. [Citation Graph (0, 0)][DBLP ] Journal ] John D. Davis , Stephen E. Richardson , Charis Charitsis , Kunle Olukotun A chip prototyping substrate: the flexible architecture for simulation and testing (FAST). [Citation Graph (0, 0)][DBLP ] Journal ] Neil Vachharajani , Matthew Iyer , Chinmay Ashok , Manish Vachharajani , David I. August , Daniel A. Connors Chip multi-processor scalability for single-threaded applications. [Citation Graph (0, 0)][DBLP ] Journal ] Julia Chen , Philo Juang , Kevin Ko , Gilberto Contreras , David Penry , Ram Rangan , Adam Stoler , Li-Shiuan Peh , Margaret Martonosi Hardware-modulated parallelism in chip multiprocessors. [Citation Graph (0, 0)][DBLP ] Journal ] Jack Sampson , Rubén González , Jean-Francois Collard , Norman P. Jouppi , Mike Schlansker Fast synchronization for chip multiprocessors. [Citation Graph (0, 0)][DBLP ] Journal ] Anahita Shayesteh , Glenn Reinman , Norman P. Jouppi , Suleyman Sair , Timothy Sherwood Dynamically configurable shared CMP helper engines for improved performance. [Citation Graph (0, 0)][DBLP ] Journal ] Theofanis Constantinou , Yiannakis Sazeides , Pierre Michaud , Damien Fetis , André Seznec Performance implications of single thread migration on a chip multi-core. [Citation Graph (0, 0)][DBLP ] Journal ] Milo M. K. Martin , Daniel J. Sorin , Bradford M. Beckmann , Michael R. Marty , Min Xu , Alaa R. Alameldeen , Kevin E. Moore , Mark D. Hill , David A. Wood Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. [Citation Graph (0, 0)][DBLP ] Journal ] David Wang , Brinda Ganesh , Nuengwong Tuaycharoen , Kathleen Baynes , Aamer Jaleel , Bruce L. Jacob DRAMsim: a memory system simulator. [Citation Graph (0, 0)][DBLP ] Journal ] Barry Rountree , Robert Springer , David K. Lowenthal , Vincent W. Freeh Notes from HPPAC 2005. [Citation Graph (0, 0)][DBLP ] Journal ] H. C. Wang , C. K. Yuen A general framework to build new CPUs by mapping abstract machine code to instruction level parallel execution hardware. [Citation Graph (0, 0)][DBLP ] Journal ] Nana B. Sam , Martin Burtscher Improving memory system performance with energy-efficient value speculation. [Citation Graph (0, 0)][DBLP ] Journal ] Mark Thorson Internet Nuggets. [Citation Graph (0, 0)][DBLP ] Journal ] 